Add mseccfg/mseccfgh CSRs, gated on the extensions that define them

config/shared/config-shared.vh

@@ -34,6 +34,10 @@ localparam logic A_SUPPORTED = (ZAAMO_SUPPORTED & ZALRSC_SUPPORTED);
 localparam logic B_SUPPORTED = ((ZBA_SUPPORTED & ZBB_SUPPORTED & ZBS_SUPPORTED));
 localparam logic C_SUPPORTED = ZCA_SUPPORTED & (D_SUPPORTED ? ZCD_SUPPORTED : 1) & (F_SUPPORTED ? ((XLEN == 32) ? ZCF_SUPPORTED : 1) : 1);
 localparam logic ZKN_SUPPORTED = (ZBKB_SUPPORTED & ZBKC_SUPPORTED & ZBKX_SUPPORTED & ZKND_SUPPORTED & ZKNE_SUPPORTED & ZKNH_SUPPORTED);
+// mseccfg/mseccfgh exist only when an extension defining one of their fields is implemented
+// (Smepmp, Zkr, Zicfilp, Smmpm); otherwise accesses raise illegal instruction.
+// Wally supports none of them yet.  Replace the 0 with the OR of those parameters as they are added.
+localparam logic MSECCFG_SUPPORTED = 0; // SMEPMP_SUPPORTED | ZKR_SUPPORTED | ZICFILP_SUPPORTED | SMMPM_SUPPORTED
 
 // Configure MISA based on supported extensions
 localparam MISA = {6'b0, 5'b0, U_SUPPORTED, 1'b0, S_SUPPORTED, 1'b0, Q_SUPPORTED, 3'b0, M_SUPPORTED, 3'b0, I_SUPPORTED, 2'b0,

config/shared/parameter-defs.vh

@@ -18,6 +18,7 @@ localparam cvw_t P = '{
   ZFH_SUPPORTED :        ZFH_SUPPORTED,
   ZFA_SUPPORTED :        ZFA_SUPPORTED,
   SSTC_SUPPORTED :       SSTC_SUPPORTED,
+  MSECCFG_SUPPORTED :    MSECCFG_SUPPORTED,
   SMSTATEEN_SUPPORTED :  SMSTATEEN_SUPPORTED,
   SSSTATEEN_SUPPORTED :  SSSTATEEN_SUPPORTED,
   SMP1P13_SUPPORTED :    SMP1P13_SUPPORTED,

src/cvw.sv

@@ -53,6 +53,7 @@ typedef struct packed {
   logic         ZFH_SUPPORTED;
   logic         ZFA_SUPPORTED;
   logic         SSTC_SUPPORTED;
+  logic         MSECCFG_SUPPORTED;
   logic         SMSTATEEN_SUPPORTED;
   logic         SSSTATEEN_SUPPORTED;
   logic         SMP1P13_SUPPORTED;

src/privileged/csrm.sv

@@ -59,6 +59,7 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   logic [P.XLEN-1:0]               MISA_REGW, MHARTID_REGW;
   logic [P.XLEN-1:0]               MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW;
   logic [P.XLEN-1:0]               MENVCFGH_REGW;
+  logic [63:0]                     MSECCFG_REGW;
   logic [P.XLEN-1:0]               TVECWriteValM;
   logic                            WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
   logic                            WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
@@ -98,6 +99,8 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   // .. up to 15 more at consecutive addresses
   localparam PMPADDR0      = 12'h3B0;
   // ... up to 63 more at consecutive addresses
+  localparam MSECCFG       = 12'h747;
+  localparam MSECCFGH      = 12'h757;
   /* verilator lint_off UNUSEDPARAM */
   localparam TSELECT       = 12'h7A0;
   localparam TDATA1        = 12'h7A1;
@@ -234,6 +237,55 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
     assign MENVCFGH_REGW = '0;
   end
 
+  // MSECCFG register
+  // mseccfg is 64 bits wide even in RV32, where the upper half is accessed as mseccfgh.
+  // It exists only if an extension defining one of its fields is implemented (P.MSECCFG_SUPPORTED);
+  // otherwise mseccfg and mseccfgh are illegal.  Wally does not yet support any of those
+  // extensions, so every field is presently read-only 0.  Uncomment the terms below as each
+  // extension is added.
+  // Note that the Smepmp fields also need sticky/locking behavior: MML and MMWP cannot be
+  // cleared once set, and RLB cannot be set once any pmpcfg entry has its L bit set, both
+  // until a PMP reset.
+  if (P.MSECCFG_SUPPORTED) begin:mseccfg
+    logic        WriteMSECCFGM;
+    logic [63:0] MSECCFG_WriteValM;
+    logic [63:0] MSECCFG_PreWriteValM;
+//  logic [1:0]  LegalizedPMM;
+
+    assign WriteMSECCFGM = CSRMWriteM & (CSRAdrM == MSECCFG);
+    // PMM is a WARL field: 00 = disabled, 10 = PMLEN 7, 11 = PMLEN 16, and 01 is reserved.
+    // Smmpm requires the largest supported address to fit in XLEN-PMLEN bits, so PMLEN 16 is
+    // unavailable with Sv57 or PA_BITS > 48.  Illegal writes keep the old value, as menvcfg.CBIE does.
+//  localparam PMLEN16_OK = !P.SV57_SUPPORTED & (P.PA_BITS <= 48);
+//  assign LegalizedPMM = ((MSECCFG_PreWriteValM[33:32] == 2'b01) |                 // reserved encoding
+//                         (MSECCFG_PreWriteValM[33:32] == 2'b11 & !PMLEN16_OK)) ?  // PMLEN 16 too wide
+//                        MSECCFG_REGW[33:32] : MSECCFG_PreWriteValM[33:32];
+    assign MSECCFG_WriteValM = {
+      30'b0,                                                       // 63:34 WPRI
+       2'b0,  // LegalizedPMM & {2{P.SMMPM_SUPPORTED & (P.XLEN==64)}}, // 33:32 PMM (Smmpm); read-only 0 on RV32
+      21'b0,                                                       // 31:11 WPRI
+       1'b0,  // MSECCFG_PreWriteValM[10] & P.ZICFILP_SUPPORTED,   //    10 MLPE (Zicfilp)
+       1'b0,  // MSECCFG_PreWriteValM[9]  & P.ZKR_SUPPORTED & P.S_SUPPORTED, // 9 SSEED (Zkr)
+       1'b0,  // MSECCFG_PreWriteValM[8]  & P.ZKR_SUPPORTED & P.U_SUPPORTED, // 8 USEED (Zkr)
+       5'b0,                                                       //   7:3 WPRI
+       1'b0,  // MSECCFG_PreWriteValM[2]  & P.SMEPMP_SUPPORTED,    //     2 RLB  (Smepmp)
+       1'b0,  // MSECCFG_PreWriteValM[1]  & P.SMEPMP_SUPPORTED,    //     1 MMWP (Smepmp)
+       1'b0   // MSECCFG_PreWriteValM[0]  & P.SMEPMP_SUPPORTED     //     0 MML  (Smepmp)
+    };
+    if (P.XLEN == 64) begin
+      assign MSECCFG_PreWriteValM = CSRWriteValM;
+      flopenr #(P.XLEN) MSECCFGreg(clk, reset, WriteMSECCFGM, MSECCFG_WriteValM, MSECCFG_REGW);
+    end else begin // RV32 has high and low halves
+      logic WriteMSECCFGHM;
+      assign MSECCFG_PreWriteValM = {CSRWriteValM, CSRWriteValM};
+      assign WriteMSECCFGHM = CSRMWriteM & (CSRAdrM == MSECCFGH);
+      flopenr #(P.XLEN) MSECCFGreg(clk, reset, WriteMSECCFGM, MSECCFG_WriteValM[31:0], MSECCFG_REGW[31:0]);
+      flopenr #(P.XLEN) MSECCFGHreg(clk, reset, WriteMSECCFGHM, MSECCFG_WriteValM[63:32], MSECCFG_REGW[63:32]);
+    end
+  end else begin
+    assign MSECCFG_REGW = '0;
+  end
+
   // MSTATEEN0 register
   // Each bit controls access from less-privileged modes to the state named by the bit; a bit is
   // read-only zero when Wally does not implement that state.  mstateen1-3 are read-only zero, which
@@ -327,6 +379,10 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
       MENVCFGH:      if (P.U_SUPPORTED & P.XLEN==32) CSRMReadValM = MENVCFGH_REGW;
                      else IllegalCSRMAccessM = 1'b1;
       MCOUNTINHIBIT: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
+      MSECCFG:       if (P.MSECCFG_SUPPORTED) CSRMReadValM = MSECCFG_REGW[P.XLEN-1:0];
+                     else IllegalCSRMAccessM = 1'b1;
+      MSECCFGH:      if (P.MSECCFG_SUPPORTED & P.XLEN==32) CSRMReadValM = MSECCFG_REGW[63:32];
+                     else IllegalCSRMAccessM = 1'b1;
       MSTATEEN0:     if (P.SMSTATEEN_SUPPORTED) CSRMReadValM = MSTATEEN0_REGW[P.XLEN-1:0];
                      else IllegalCSRMAccessM = 1'b1;
       MSTATEEN1,

testbench/common/wallyTracer.sv

@@ -217,12 +217,17 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
     // Machine Information Registers and Configuration CSRs
     `CONNECT_CSR(MISA, 12'h301, testbench.dut.core.priv.priv.csr.csrm.MISA_REGW);
     `CONNECT_CSR(MENVCFG, 12'h30A, testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW);
-    `CONNECT_CSR(MSECCFG, 12'h747, 0); // mseccfg
     `CONNECT_CSR(MVENDORID, 12'hF11, 0); //mvendorid
     `CONNECT_CSR(MARCHID, 12'hF12, 0); // marchid
     `CONNECT_CSR(MIMPID, 12'hF13, {{P.XLEN-12{1'b0}}, 12'h100}); // mimpid
     `CONNECT_CSR(MHARTID, 12'hF14, testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW);
     `CONNECT_CSR(MCONFIGPTR, 12'hF15, 0); //mconfigptr
+    if (P.MSECCFG_SUPPORTED) begin
+      `CONNECT_CSR(MSECCFG, 12'h747, testbench.dut.core.priv.priv.csr.csrm.MSECCFG_REGW[P.XLEN-1:0]);
+      if (P.XLEN == 32) begin
+        `CONNECT_CSR(MSECCFGH, 12'h757, testbench.dut.core.priv.priv.csr.csrm.MSECCFG_REGW[63:32]);
+      end
+    end
 
     // Smstateen CSRs.  mstateen1-3 are read-only zero, as are the bits of mstateen0 whose state
     // Wally does not implement.
@@ -268,7 +273,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
     if (P.XLEN == 32) begin
       `CONNECT_CSR(MSTATUSH, 12'h310, testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW);
       `CONNECT_CSR(MENVCFGH, 12'h31A, testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW);
-      `CONNECT_CSR(MSECCFGH, 12'h757, 0); // mseccfgh
     end
   end