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Add mseccfg/mseccfgh CSRs, gated on the extensions that define them - #1891
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The tracer reported both CSRs as literal 0, which is right only while every field is read-only zero. Connect it to MSECCFG_REGW so that enabling a field later cannot silently leave lockstep comparing against a stale constant. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
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General question. What is Wally's default behavior for non-existing CSRs? I thought it was to raise an illegal-instruction exception and since mseccfg requires at least one of three extensions should a read of these two CSRs cause an illegal-instruction exception if non of these extensions exist? |
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Wally implements Ssstrict in its rv64/32gc configs, which requires raising an illegal instruction for any CSR that is not implemented. Agreed that we should continue to throw an illegal instruction exception for mseccfg when Zkr/Smepmp/etc. are not implemented. |
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Agreed. Will fix. |
mseccfg/mseccfgh exist only if Smepmp, Zkr, Zicfilp or Smmpm is implemented; otherwise accesses are illegal. Add a derived MSECCFG_SUPPORTED parameter (presently 0, since Wally supports none of those extensions) that gates the register, the CSR read decode and the tracer connections. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
# Conflicts: # config/shared/parameter-defs.vh # src/cvw.sv # src/privileged/csrm.sv
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Adds the
mseccfg(0x747) andmseccfgh(0x757) CSRs tocsrm.sv, implemented only when an extension that defines a field in them is present.The privileged spec defines
mseccfgonly for Smepmp, Zkr, Zicfilp and Smmpm. A new derived parameterMSECCFG_SUPPORTEDinconfig-shared.vhgates the register, the CSR read decode and the tracer connections. When it is 0, both addresses raise an illegal instruction exception, as they did before this PR, and no flops are generated. Wally does not yet implement any of those extensions, soMSECCFG_SUPPORTEDis presently 0, with the intended OR of the extension parameters commented beside it. When it is set, every field is read-only 0 until the extensions are added.mseccfgis 64 bits wide even on RV32, where the upper half is reached throughmseccfgh; the register is split into low/high flops on RV32 following the existingmenvcfg/menvcfghpattern.mseccfghreads the high half on RV32 and traps illegal on RV64.1'b0constant with the enabling term commented out beside it, so turning a field on later is a pure uncomment:P.SMMPM_SUPPORTED & (P.XLEN==64)P.ZICFILP_SUPPORTEDP.ZKR_SUPPORTED & P.S_SUPPORTEDP.ZKR_SUPPORTED & P.U_SUPPORTEDP.SMEPMP_SUPPORTEDP.SMEPMP_SUPPORTEDP.SMEPMP_SUPPORTEDNone of those config parameters exist yet; they come with the extensions.
Two WARL/legalization requirements are captured in comments so they are not missed later:
01reserved, and Smmpm requires the largest supported address to fit inXLEN-PMLENbits, so PMLEN 16 (11) is unavailable with Sv57 orPA_BITS > 48— which includes the currentrv64gcconfig. The commentedLegalizedPMMkeeps the old value on an illegal write, matching themenvcfg.CBIEconvention already in this file.pmpcfgentry has its L bit set, both until a PMP reset.wallyTracer.svconnectsmseccfg/mseccfghto the register only whenMSECCFG_SUPPORTED; otherwise they are not traced.Testing
lint-wallypasses on all standard configs plusfdqh_rv64gc, both as committed (MSECCFG_SUPPORTED = 0) and withMSECCFG_SUPPORTEDtemporarily set to 1 so the gated register logic is also linted. With the parameter at 0, behavior is unchanged fromrva23: both addresses still trap. No directed test was added; one belongs with the first extension that enables the register.🤖 Generated with Claude Code