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theteamonk/README.md

Logo

Hey! I am Chaitra

Hope you coverage all my repos. Welcome!

🚀 About Me

Hello there, I'm a Design Verification Engineer, and have a keen interest in anything and everthing VLSI! I am a working professional and currently working on project(s) and exploring.

🛠 Languages and Tools

  • Verilog
  • System Verilog
  • UVM
  • Xilinx Ise
  • Cadence Xcelium
  • Cadence SimVision
  • vManager
  • QuestaSim
  • Synopsys VCS
  • Cadence Virtuoso

Top Langs

🔗 Links

portfolio linkedin

Verification_Academy

edaplayground

Thank you for visiting

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  1. Dual-Port-RAM-4096x64 Dual-Port-RAM-4096x64 Public

    Dual Port RAM - Verification in System Verilog and Functional Coverage

    SystemVerilog 1

  2. router1x3 router1x3 Public

    Router 1x3 Design and Verification in Verilog

    Verilog