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Internal assertion when using conditional operator with strings inside a task #1459
Description
Version
Icarus Verilog version 13.0 (stable) (v13_0)
Command
iverilog -g2012 test.svTest case
module test;
string a = "A";
string b = "B";
task t(input int verbosity);
string color;
color = (verbosity >= 3) ? a : b;
endtask
endmoduleActual result
Assertion failed: ivl_expr_value(expr) == IVL_VT_BOOL ||
ivl_expr_value(expr) == IVL_VT_VECTOR,
file ../../iverilog-13_0/tgt-vvp/eval_vec4.c, line 1359
Expected result
The code should either compile successfully or produce a normal diagnostic if the construct is unsupported. It should not terminate with an internal assertion.
Workaround
Replacing the conditional operator with if/else avoids the assertion:
if (verbosity >= 3)
color = a;
else
color = b;
Activity
caryr commentedon Aug 4, 2026
This is an issue with the ternary operator. It may be related to #1298
[test] Add regression for GH1459 string ternary in task
[test] Add regression for GH1459 string ternary in task
[test] Cover GH1459 string conditional inside a task
Add test for github #1459
caryr commentedon Sep 27, 2026
This is fixed along with #1298 in the repo HEAD.