feat: add SD overclocking support for DIGIC 4 SD bodies - #291
Conversation
- Adjusts PLL1 (that clocks the SD card) to generate 72Mhz or 92Mhz clocks, instead of the standard 24Mhz / 48Mhz (lo/hi speed)
|
This is awesome. Kind of late night here, but I picked the test build from your other ticket and tested SDCard with my T3i. 5min SDCard test:
Lexar Silver Plus 256GB, LMSSIPL256G-BNABU Looks like my MLVApp doesn't like the compressed raws, but I was able to shoot a whole 9s of 1280x720 14bit (uncompressed) 29.97fps.... way better than before. I'll take the camera on a wander tomorrow to test out some other settings. |
|
PS. I also have a T2i if you want me to test that too... ;-) |
|
Please be aware that this is not thoroughly tested and will have higher risk than a normal build!
Can you describe "doesn't like" in more detail? Is there an error message? What behaviour do you see? |
|
@reticulatedpines Understood, camera (and/or hair) may burst into flames without warning. I was incorrect about MLVApp. It threw an error with one of my (corrupt) files. Otherwise 1st frame of 14bit-lossess is junk, but the rest are OK. Off to shoot more... |
|
Right, that's what I noticed too, I think I need to increase the number of warm-up frames. It sometimes is 4, some other times it is 6, but I guess it can sometimes be longer.... (or I can find out what is causing this warm-up corruption 🤣) |
|
Re getting this code into the repo, the best way is probably to integrate both this code, and the 200D code in sd.c into sd_uhs module, then rename that module sd_clock (since it has three different methods to change SD clock, and they're not all UHS related). Do you want to do that for this code? That way you get your name on it. If you don't care, I can do all of it, though it likely won't happen this month. |
|
Yup, sounds good, I will prepare the mod 👍 |
Hoist the nine near-identical is_camera() init blocks into a uhs_cams[] table (ROM addresses, family, pauses_rw, sdr160_preset, has_safe_mode, menu variant). Dispatch the four overclock-task bodies on family instead of re-checking is_camera(). Unsupported bodies no longer get a Prefs menu entry, so a DIGIC 4 backend can later own the same slot. Co-authored-by: Cursor <cursoragent@cursor.com>
Split the module into digic5_uhs (UHS registers + ROM hooks) and digic4_pll (PLL1 root divider, no ROM addresses), dispatched from a thin sd_uhs.c glue on get_digic_version(). Remove the always-on core sd_overclock.c; DIGIC 4 SD bodies now get the feature as an opt-in module under Prefs. Ship sd_uhs in modules.included for 500D, 550D, 600D, 60D, and 1100D. Menu help marks 72/96 MHz as verified only on 600D; other bodies rely on write/read verify + auto-revert. Co-authored-by: Cursor <cursoragent@cursor.com>
0eb5d53 to
7cbfe4d
Compare
The module is no longer UHS-specific: DIGIC 4 uses a PLL1 root-clock backend. Rename directory, MODULE_NAME, entry file, modules/Makefile, all modules.included entries, README, and the stale 200D features.h comment. Existing ML/SETTINGS/sd_uhs.cfg and sd_uhs.en are orphaned; users re-enable once under the new name. Co-authored-by: Cursor <cursoragent@cursor.com>
7cbfe4d to
ed295ee
Compare
|
Pushed the conversion into a module. Folded Digic 5 and Digic 4 versions into the same module (now named Once loaded you can find the menu option on prefs: Tested on EOS 600D, looking for testers for other cameras 😄 Here are some new builds (Digic 4): And some for Digic 5 (for validation): Let me know if you need any specific build for your camera |
|
Here you go... got lazy and ran the 1minute benchmark. |
3 participants
This PR adds a new Debug menu option that appears on DIGIC 4 bodies with an SD card and enables overclocking the SD controller itself.
Normally SDHC cards operate at a maximum of 48 MHz in High-Speed mode. Newer UHS-class cards are capable of higher clocks, but they usually do so in a UHS configuration at 1.8 V for better signal integrity. This change stays in the High-Speed path and instead raises the SD root clock (PLL1) above Canon's 48 MHz setting. PLL1 seems not to clock any other domains of the camera, making this a relatively safe addition.
The menu offers 48 / 72 / 96 / 144 MHz. An overclock at 72 MHz gives about 1.5× throughput, and at 96 MHz about 2×. Signal integrity is not guaranteed the higher you go - 144 MHz is labeled DANGER and wedged the SD driver on the card used for testing (with a dirty-flag recovery path that resets to stock after a failed boot). But you might have better luck with yours.
Settings are applied at boot after DryOS finishes card bring-up; a restart is required after changing the menu. Post-apply write/read verification refuses to keep a broken clock, and the feature self-disables if PLL1 is not the expected stock word at init (so it stays inert on unexpected silicon).
Benchmarked ~40 MB/s on an EOS 600D (with a SanDisk Extreme 128GB):
Notes
CONFIG_DIGIC_IV && !CONFIG_CF_SLOT(500D / 550D / 600D / 60D / 1100D). Distinct from the existing Digic 5+sd_uhsmodule.