WORKAROUND: Restore misco0 register on CPU idle exit#1362
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CPU system registers are reset on entry to the idle state, which clears the required bits in the misc0 cnd ctrl register and prevents CE/UE interrupts from firing. Register a PM notifier to restore the misc0 and ctrl registers on idle exit, ensuring that interrupts are correctly triggered. This is a temporary workaround and will be reverted once the proper fix is upstreamed in v2 of this series. Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
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CPU system registers are reset on entry to the idle state, which clears the required bits in the misc0 cnd ctrl register and prevents CE/UE interrupts from firing.
Register a PM notifier to restore the misc0 and ctrl registers on idle exit, ensuring that interrupts are correctly triggered.
This is a temporary workaround and will be reverted once the proper fix is upstreamed in v2 of this series.