VME v0.4 update by boboloiono · Pull Request #177 · pulp-platform/spatz

boboloiono · 2026-10-22T19:47:13Z

SW:

update llvm-project, riscv-opcodes
add fp16 gemm kernels (unit, alpha, beta)
vq-matmul, matmul-softmax is still ongoing

HW:

add use_instruction_buffer in doublebw_config
remove Compute core in doublebw_config
modified V2T, T2V mover to keep vrf request high

Lint:

remove combinational loops
remove automatic declaration initializers

Documentation:

add ope/docs (including micro-architecture section)

Separate the logical tile-row capacity from the VLSU–OPE Tile transfer word by introducing TileRowBWidth, TileWordBWidth, tile_word_t, and a word-relative column offset in Tile requests. 1. Extend the double-bandwidth VLSU with word_col-based segmentation so row-oriented accesses can gather and commit a logical tile row over multiple Tile words, and update column-oriented accesses to select the containing Tile word and use a word-local column offset for correct gather and scatter behavior. 2. Update the OPE Tile interface to consume and produce tile_word_t data, and use the request column offset and element count to gather or scatter the corresponding accumulator segment while preserving TEW-dependent byte and half-word updates. Currently, TileWordBWidth equals TileRowBWidth (TileEdge × AccElemBytes), preserving full-row transfers. The separated types and segmented control path allow a future fixed 512-bit Tile port by setting TileWordBWidth to 2 × OPEComputeEdge × AccElemBytes while retaining the same logical tile-row traversal.

The base vector group now carries both paired reduction rows under LMUL=2, so the kernels halve the operand-load and MAC instruction compared to TE16.

v0: mt0 row 0 | v1 mt4 row0 | v2 mt8 row0 | v3 mt12 row0 => vsetvl e32 m4 + vse32 v0 v4: mt0 row 1 v8: mt0 row 2

…e-parameters - compiler-determined chunk M, N=64 in enum - optimize fp32 matmul vse 1x4 tile kernel (no cross-block gets 78%)

… (76.6%) v16->v24->v16->v24 instead of v16->v20->v24->v28 (because in tk=2 vtfmm reads from v24, v28) v16 | v24 | v16 | v24 v0 mt0 | mt4 | mt8 | mt12

…vtse (65%) 1. vtfmm (x*w) -> vtmv -> vle b + vfadd -> vse 2. vtle -> vtfmm -> vtse

…m mt12 to mt0 compute (73%) - gemm-alpha gets 28 cycles less than gemm-unit via vtzero -> vtfmm -> vtmv -> vle bias + vfmacc.vf -> vse

Separate the logical tile-row capacity from the VLSU–OPE Tile transfer word by introducing TileRowBWidth, TileWordBWidth, tile_word_t, and a word-relative column offset in Tile requests. 1. Extend the double-bandwidth VLSU with word_col-based segmentation so row-oriented accesses can gather and commit a logical tile row over multiple Tile words, and update column-oriented accesses to select the containing Tile word and use a word-local column offset for correct gather and scatter behavior. 2. Update the OPE Tile interface to consume and produce tile_word_t data, and use the request column offset and element count to gather or scatter the corresponding accumulator segment while preserving TEW-dependent byte and half-word updates. Currently, TileWordBWidth equals TileRowBWidth (TileEdge × AccElemBytes), preserving full-row transfers. The separated types and segmented control path allow a future fixed 512-bit Tile port by setting TileWordBWidth to 2 × OPEComputeEdge × AccElemBytes while retaining the same logical tile-row traversal.

The base vector group now carries both paired reduction rows under LMUL=2, so the kernels halve the operand-load and MAC instruction compared to TE16.

- ope, pkg: rename TE/CE as NrAccPerComputeElem

tcdm size=128KB supports fp16->fp32 M64_N64_K128 tcdm size=256KB supports fp16->fp32 M64_N64_K128, K256

… SystemVerilog tools may reject.

Decouple MAC request eligibility and pipeline-result draining from same-cycle VRF handshakes to eliminate feedback through operand arbitration and scheduler bypass logic. Simplify buffered VLSU writeback selection so FIFO draining depends only on registered occupancy and VRF acceptance. Use statically bounded tile-to-vector packing and shift-based vector-to-tile extraction to avoid out-of-range part selects during synthesis. SpyGlass reports no remaining combinational-loop violations or synthesis errors.

…d decoder Split block-local declaration initializers into explicit assignments before use. This makes the combinational data flow visible to SpyGlass and removes the W123 read-but-never-set errors for decoder requests and scoreboard IDs.

factor version (α/β) × XW + bias achieves only 66.59% (removed)

…odings Update the generated instruction patterns and decode msetmtype and msetmtypei separately, including the new altfmt immediate bit. Accept valid matrix tile element widths in the controller.

- organize matrix configuration and operation test coverage - run FP32 vtfmm cases before FP16-to-FP32 cases - document test cases and disabled formats consistently - cover row and column tile transfers

Preserve TEW8 element indices across a complete tile word and prevent dependent MAC bypass before forwarding is available.

- update llvm-project, riscv-opcodes (supports v0.4 and vlxblk) - current Makefile excludes opcodes-vlxblk_CUSTOM

- update fp16 vse store-group mamtul with same vector access order as gemm, reducing 367 cycles

M64 N64 K128 CB_D 8, 2 cb of 256)

- removed vfredmax, vfredsum - applied CT = BT * AT and algorithm Macros prepared in include/ope_transformaner.h to represent 1/x, 1/sqrt(x), exp(), log() in RVV

boboloiono added 30 commits October 16, 2026 11:23

[sw] fp16 matmul vtse: remove TE32 row-stride operand

c43011b

The base vector group now carries both paired reduction rows under LMUL=2, so the kernels halve the operand-load and MAC instruction compared to TE16.

[sw] add fp16-matmul vse "store-group" strategy via 1x4 tiles layout

4316d23

v0: mt0 row 0 | v1 mt4 row0 | v2 mt8 row0 | v3 mt12 row0 => vsetvl e32 m4 + vse32 v0 v4: mt0 row 1 v8: mt0 row 2

[sw] optimal kernel matmul(*A, *B, *C) without passing M, N, K runtim…

fab3193

…e-parameters - compiler-determined chunk M, N=64 in enum - optimize fp32 matmul vse 1x4 tile kernel (no cross-block gets 78%)

[sw] fp16 matmul vse with 1x4 via change vector load register mapping…

b2ded3d

… (76.6%) v16->v24->v16->v24 instead of v16->v20->v24->v28 (because in tk=2 vtfmm reads from v24, v28) v16 | v24 | v16 | v24 v0 mt0 | mt4 | mt8 | mt12

[sw] fp16 gemm with vle+vse using 1x4 layout (66%), vsetvl with vtle+…

8ad10c2

…vtse (65%) 1. vtfmm (x*w) -> vtmv -> vle b + vfadd -> vse 2. vtle -> vtfmm -> vtse

[sw] fp16 gemm LMUL=8 for bias vle32, vfadd, vse32 (66.5%)

3f65680

[sw] gemm-unit, gemm-alpha: ungroup vle v0 to remove 2 cycle gaps fro…

a8d721e

…m mt12 to mt0 compute (73%) - gemm-alpha gets 28 cycles less than gemm-unit via vtzero -> vtfmm -> vtmv -> vle bias + vfmacc.vf -> vse

[sw] fp16 matmul vtse: remove TE32 row-stride operand

775faf7

The base vector group now carries both paired reduction rows under LMUL=2, so the kernels halve the operand-load and MAC instruction compared to TE16.

[hw] controller, vlsu: memory operations use EEW instead of SEW

9922553

- ope, pkg: rename TE/CE as NrAccPerComputeElem

[build] allow sw.vsim to select TE32 VME kernels

1b5698e

[sw] passing TCDM size parameter with runtime config SNRT_TCDM_SIZE

e901d21

[sw] modify fp16 kernel size generation

f4c7819

tcdm size=128KB supports fp16->fp32 M64_N64_K128 tcdm size=256KB supports fp16->fp32 M64_N64_K128, K256

[hw] ope: remove non-standard forward references (typedef) that newer…

ba0cbbd

… SystemVerilog tools may reject.

[sw] gemm-beta: α XW + β bias (66.85%).

50433d0

factor version (α/β) × XW + bias achieves only 66.59% (removed)

[hw] decoder, controller riscv_instr: Align VME v0.4 with updated enc…

eddb074

…odings Update the generated instruction patterns and decode msetmtype and msetmtypei separately, including the new altfmt immediate bit. Accept valid matrix tile element widths in the controller.

[vme] Remove obsolete FP32 GEMM variants

daa0f68

[vme] Rework Zvt v0.4 ISA tests

d29f527

- organize matrix configuration and operation test coverage - run FP32 vtfmm cases before FP16-to-FP32 cases - document test cases and disabled formats consistently - cover row and column tile transfers

[HW] Fix OPE tile-word indexing and MAC forwarding

ccb1d83

Preserve TEW8 element indices across a complete tile word and prevent dependent MAC bypass before forwarding is available.

[hw] spatz_cluster: remove compute core from doublebw config

ce18160

[hw] ope: pipeline back-to-back tile-vector moves

149847e

[sw] vme: update Zvt v0.4 software support

5de5c61

[hw] ope: document VME microarchitecture

16299d1

[docs] remove Chinese VME microarchitecture draft

271968d

[hw] modification for vme_v0.4 backend (tcdm=128 KiB, one core)

78f1c52

- update llvm-project, riscv-opcodes (supports v0.4 and vlxblk) - current Makefile excludes opcodes-vlxblk_CUSTOM

[sw] fp16 vq-mamtul with vluxei16 (14.51%)

6ebaef0

- update fp16 vse store-group mamtul with same vector access order as gemm, reducing 367 cycles

[sw] vq-gemm in VME speedup 1.8x compared to O-POPE benchmark

b6c5fa1

M64 N64 K128 CB_D 8, 2 cb of 256)

boboloiono added 2 commits October 25, 2026 20:30

[sw] gemm-softmax in VME gets 1.44x speedup

b8240aa

- removed vfredmax, vfredsum - applied CT = BT * AT and algorithm Macros prepared in include/ope_transformaner.h to represent 1/x, 1/sqrt(x), exp(), log() in RVV

vme: remove obsolete FP32 VLE/VTLE matmul apps

54f6c8f

Navigation Menu

Repository navigation

VME v0.4 update - #177

VME v0.4 update#177
boboloiono wants to merge 32 commits into
pulp-platform:pei/vmefrom
boboloiono:vme_v0.4

boboloiono commented Oct 22, 2026 •

edited

Loading

Uh oh!

Reviewers

Uh oh!

Assignees

Labels

Projects

Milestone

Development

Uh oh!

1 participant

Conversation

boboloiono commented Oct 22, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

Reviewers

Uh oh!

Assignees

Labels

Projects

Milestone

Development

Uh oh!

1 participant

boboloiono commented Oct 22, 2026 •

edited

Loading