Fix: adapt host build graph swimlane clock alignment - #2244
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Included review availability: Your plan provides up to 1 included review per hour; 0 remain after this review. 📝 WalkthroughWalkthroughThe change adds persisted Host/device clock alignment for eligible single-file captures. It adds scheduler-stream containment, alignment metadata and fallback behavior, updated profiling documentation, diagnostic logging, and tests for legacy, HBG, device-only, and invalid-input cases. ChangesHost/device clock alignment
Priority: ⬇️ Low Estimated code review effort: 4 (Complex) | ~45 minutes Change: Bug fix Sequence Diagram(s)sequenceDiagram
participant Capture as Single-file capture
participant Converter as swimlane_converter
participant Logs as Host logs
participant Metadata as metadata.clock_alignment
Capture->>Converter: Prepare or reuse alignment
Converter->>Logs: Match Host records when no valid saved mapping exists
Logs-->>Converter: Host anchors and timing bounds
Converter->>Metadata: Persist validated mapping atomically
Converter-->>Capture: Decode with aligned or fallback timestamps
Merge Risk: ⚪ Minimal · up to The alignment, containment, fallback, and persistence paths have corresponding validation coverage, with no actionable merge-blocking issue identified. 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
Full details: Docstring CoverageExplanation Docstring coverage is 31.11% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 45 functions across 6 files. (4 skipped: 4 unsupported.)
✨ Finishing Touches 💡 1🛠️ Fix failing CI checks 💡
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Support host_build_graph swimlane captures containing Host records, including level-4 captures and level-3 captures with Host phase recording enabled. Align Host Orchestrator and device records on a bounded timeline, and store the mapping in the source JSON for converters and IDE readers. - Read versioned Scheduler streams, include all device producers in the containment extent, and join AICPU streams to logged scheduler phases. Name AICore Scheduler lanes by worker ID to match Worker View. - Emit invocation-correlated AICPU-launch markers at TIMING and use them to constrain device placement within the Host runner window. - Export host_clock_alignment.<pid>.log beside each eligible capture during native finalize, covering direct L2 calls and persistent ChipWorker runs. Read the cumulative log tail from the invocation's starting offset, filter by PID and invocation, flush the process logger, and publish the capture-local timing log atomically before run completion. - Keep the live Host logger bound to its first configured directory. Support flushing through runtime DSOs borrowing the process logger, and flush ChipWorker logs before task completion when chip-swimlane is enabled. - Match capture invocations using dispatch identities, Host PIDs, and Host-record bounds, including zero synchronous dispatch IDs. - Store alignment status, device/Host anchors, and allowed Host bounds in metadata.clock_alignment while preserving raw timestamps and formatting. Reuse valid mappings and recalculate when explicit Host logs are supplied. - Apply alignment during single-file conversion and directory merging. Warn on missing or ambiguous inputs and retain unaligned diagnostic views. Support full-log inputs for general multi-rank containment. - Bind ST log drains to a pytest session directory so temporary capture cleanup and per-test retention policies cannot remove the active log sink. Use the native monotonic clock for ST log filtering. - Document the source schema, profiling behavior, and log lifecycle. Keep internal join residuals in cycles and serialize them in nanoseconds. Validation: - Focused Python alignment, converter, Worker, SceneTest, and trace API UT. - C++ logger tests, including cross-DSO flushing, and applicable pre-commit. - A5 level-4 and level-3 Host-enabled direct L2 and persistent ChipWorker ST; level-3 Device-only captures produce no compact timing log. - Consecutive captures with dependency generation and temporary-directory cleanup: complete markers, distinct invocations, and bounded conversion. Co-authored-by: majin0824 <majin15@huawei.com>
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Fix: adapt host build graph swimlane clock alignment
Support host_build_graph swimlane captures containing Host records, including
level-4 captures and level-3 captures with Host phase recording enabled.
Align Host Orchestrator and device records on a bounded timeline, and store
the mapping in the source JSON for converters and IDE readers.
containment extent, and join AICPU streams to logged scheduler phases.
Name AICore Scheduler lanes by worker ID to match Worker View.
to constrain device placement within the Host runner window.
native finalize, covering direct L2 calls and persistent ChipWorker runs.
Read the cumulative log tail from the invocation's starting offset,
filter by PID and invocation, flush the process logger, and publish the
capture-local timing log atomically before run completion.
flushing through runtime DSOs borrowing the process logger, and flush
ChipWorker logs before task completion when chip-swimlane is enabled.
Host-record bounds, including zero synchronous dispatch IDs.
metadata.clock_alignment while preserving raw timestamps and formatting.
Reuse valid mappings and recalculate when explicit Host logs are supplied.
Warn on missing or ambiguous inputs and retain unaligned diagnostic views.
Support full-log inputs for general multi-rank containment.
cleanup and per-test retention policies cannot remove the active log sink.
Use the native monotonic clock for ST log filtering.
internal join residuals in cycles and serialize them in nanoseconds.
Validation:
level-3 Device-only captures produce no compact timing log.
cleanup: complete markers, distinct invocations, and bounded conversion.
Co-authored-by: majin0824 majin15@huawei.com