A Basic High Level Synthesis System Using LLVM

Project Structure

src/ - The source code for scheduling and verilog generation
test/scheduling.cpp - Unit tests of the HLS tool
test/ll_files/ - Example programs that are synthesized in unit tests

Dependencies:

LLVM and clang
Z3 SMT solver
Icarus Verilog (to run the unit tests of generated verilog)

Build and Test Instructions

Once the dependencies are installed do:

cmake .
make -j
./all-tests

Name		Name	Last commit message	Last commit date
experiments		experiments
hlslib		hlslib
src		src
test		test
.gitignore		.gitignore
.travis.yml		.travis.yml
CMakeLists.txt		CMakeLists.txt
LICENSE		LICENSE
RAM.v		RAM.v
RAM2.v		RAM2.v
RAM3.v		RAM3.v
README.md		README.md
adder.v		adder.v
axi_ram.v		axi_ram.v
axi_rb.v		axi_rb.v
axi_read.v		axi_read.v
axi_wb.v		axi_wb.v
axi_write.v		axi_write.v
axil_ram.v		axil_ram.v
b_fifo.v		b_fifo.v
builtins.v		builtins.v
channel_reduce_4.v		channel_reduce_4.v
cmp_gt_tb.v		cmp_gt_tb.v
common_network.v		common_network.v
complex_num_tb.v		complex_num_tb.v
compound_fifo_tb.v		compound_fifo_tb.v
concat_rtl.v		concat_rtl.v
delay.v		delay.v
dff_3_pipe.v		dff_3_pipe.v
dynamic_arch_sram_class_tb.v		dynamic_arch_sram_class_tb.v
dynamic_arch_tb.v		dynamic_arch_tb.v
eth_axis_tx.v		eth_axis_tx.v
fifo.v		fifo.v
fifo_3.v		fifo_3.v
fifo_in_loop_tb.v		fifo_in_loop_tb.v
fifo_read.v		fifo_read.v
fifo_read_delay_tb.v		fifo_read_delay_tb.v
fifo_user_tb.v		fifo_user_tb.v
fifo_write.v		fifo_write.v
fpu_add.v		fpu_add.v
halide_arch_tests.txt		halide_arch_tests.txt
if_else_tb.v		if_else_tb.v
int_wrapper_tb.cpp		int_wrapper_tb.cpp
ip_eth_rx.v		ip_eth_rx.v
lb_unit_test.v		lb_unit_test.v
loop_add_4_6_iters_tb.v		loop_add_4_6_iters_tb.v
loop_add_4_copy_tb.v		loop_add_4_copy_tb.v
loop_add_4_tb.v		loop_add_4_tb.v
loop_add_7_tb.v		loop_add_7_tb.v
loop_add_tb.v		loop_add_tb.v
many_adds_tb.v		many_adds_tb.v
median.v		median.v
median_filter.v		median_filter.v
median_wires.v		median_wires.v
mvmul_tb.v		mvmul_tb.v
node.v		node.v
pixel_network.v		pixel_network.v
plus_tb.v		plus_tb.v
ram_primitives.v		ram_primitives.v
ram_read.v		ram_read.v
ram_write.v		ram_write.v
read_2_tb.v		read_2_tb.v
run_median.v		run_median.v
run_median_func.v		run_median_func.v
single_store_tb.v		single_store_tb.v
stalled_single_store_axi_tb.v		stalled_single_store_axi_tb.v
stalled_single_store_tb.v		stalled_single_store_tb.v
state_machine.v		state_machine.v
sys_array_2x2_tb.v		sys_array_2x2_tb.v
timed_wire_reduce_tb.v		timed_wire_reduce_tb.v
vhls_target_tb.v		vhls_target_tb.v
write_byte_func.v		write_byte_func.v
write_header_func.v		write_header_func.v

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Project Structure

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