Skip to content

Pull requests: diffblue/hw-cbmc

New pull request New
60 Open 1,710 Closed
60 Open 1,710 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

error message when reset constraint cannot be parsed
#1844 opened May 4, 2026 by kroening Collaborator Loading…
SMV netlists: use pretty name, when available
#1843 opened May 4, 2026 by kroening Collaborator Loading…
Verilog: grammar for classes Verilog
#1842 opened May 4, 2026 by kroening Collaborator • Draft
BTOR2 front-end
#1840 opened May 1, 2026 by kroening Collaborator Loading…
bump cbmc dependency dependencies Pull requests that update a dependency file
#1839 opened Apr 30, 2026 by kroening Collaborator • Draft
Verilog: use stronger types for case statements cleanup Verilog
#1838 opened Apr 29, 2026 by kroening Collaborator Loading…
Verilog: case generate Verilog
#1837 opened Apr 28, 2026 by kroening Collaborator Loading…
BMC: semantics of pending matches
#1836 opened Apr 28, 2026 by kroening Collaborator Loading…
5
move logic for SVA cover into the property encoding Verilog
#1827 opened Apr 24, 2026 by kroening Collaborator • Draft
New IC3/PDR engine
#1817 opened Apr 21, 2026 by kroening Collaborator • Draft
Verilog: create $root module instance
#1816 opened Apr 21, 2026 by kroening Collaborator • Draft
use FPA theory when generating SMT-LIB2 for Z3 engines
#1812 opened Apr 20, 2026 by kroening Collaborator Loading…
3
Verilog: grammar for programs Verilog
#1811 opened Apr 18, 2026 by kroening Collaborator • Draft
Verilog: multiple top-level modules Verilog
#1807 opened Apr 17, 2026 by kroening Collaborator • Draft
netlist conversion: split up vector equality constraints engines
#1802 opened Apr 12, 2026 by kroening Collaborator • Draft
BDD model checker: early variable quantification
#1801 opened Apr 9, 2026 by kroening Collaborator • Draft
Verilog: $root Verilog
#1797 opened Apr 8, 2026 by kroening Collaborator • Draft
SystemVerilog: property-typed ports for checkers Verilog
#1739 opened Mar 18, 2026 by kroening Collaborator • Draft
class interface for flex
#1695 opened Mar 4, 2026 by kroening Collaborator • Draft
2
SystemVerilog: detect import conflicts Verilog
#1693 opened Mar 3, 2026 by kroening Collaborator • Draft
2
BDD engine: project away inputs engines
#1687 opened Mar 1, 2026 by kroening Collaborator • Draft
SystemVerilog queue benchmarks Tests Verilog
#1634 opened Feb 10, 2026 by kroening Collaborator • Draft
nondet elimination for AIGs engines
#1612 opened Feb 1, 2026 by kroening Collaborator • Draft
AIG simplifier using equivalences
#1605 opened Jan 26, 2026 by kroening Collaborator • Draft
1
bv_varidt now has next member engines
#1586 opened Jan 12, 2026 by kroening Collaborator • Draft
1
ProTip! Updated in the last three days: updated:>2026-05-01.