Issues

• Potential Conflict Search Error

  byuccl/spydrnet#224 · Filter by author cjtafoya512 opened on Feb 6, 2025

• Flatten cannot handle multiple instances of one definition in another definition.

  documentation
  byuccl/spydrnet#220 · Filter by author zhuguiyuan opened on Feb 14, 2024
  2

• EDIF files generated by Atmel CPLD fitter unparsable.

  resolved?
  byuccl/spydrnet#215 · Filter by author peterzieba opened on Oct 15, 2023
  11

• Getting recursion error when parsing a netlist

  resolved?
  byuccl/spydrnet#213 · Filter by author arun-chaubey opened on Oct 5, 2023
  7

• Create CoLab examples

  documentation
  byuccl/spydrnet#207 · Filter by author wirthlin opened on May 15, 2023

• Include type hinting

  byuccl/spydrnet#203 · Filter by author agg23 opened on Apr 3, 2023
  1

• Handling Intel architecture definitions

  byuccl/spydrnet#202 · Filter by author agg23 opened on Apr 3, 2023
  1

• [verilog] Primitives

  byuccl/spydrnet#201 · Filter by author agg23 opened on Apr 2, 2023
  4

• Distinguishing pins in multi-bit ports

  resolved?
  byuccl/spydrnet#196 · Filter by author jgoeders opened on Mar 18, 2023
  5

• Delete Old Branches

  byuccl/spydrnet#192 · Filter by author jacobdbrown4 opened on Oct 19, 2022
  5

• Transformation to and from EBLIF

  byuccl/spydrnet#191 · Filter by author emonlux opened on Aug 12, 2022
  1

• Make SpyDrNet internals completely generic

  byuccl/spydrnet#185 · Filter by author jacobdbrown4 opened on Aug 2, 2022
  2

• Case Sensitivity - EDIF composer

  byuccl/spydrnet#182 · Filter by author emonlux opened on Jul 1, 2022
  10

• Setting correct top module when parsing netlist from Lattice

  resolved?
  byuccl/spydrnet#178 · Filter by author jacobdbrown4 opened on May 20, 2022
  4

• Can you store an instance's information in an HRef object?

  resolved?
  byuccl/spydrnet#155 · Filter by author jacobdbrown4 opened on Oct 14, 2021
  9

• EDIF parser pytest coverage

  byuccl/spydrnet#151 · Filter by author jacobdbrown4 opened on Aug 2, 2021

• Create a built in construct and move module/cell parameters out of the metadata

  byuccl/spydrnet#145 · Filter by author thunder-hammer opened on Jun 17, 2021
  1

• Create Xilinx library

  minor
  byuccl/spydrnet#144 · Filter by author wirthlin opened on Jun 7, 2021
  5

  

• Create a back end to support the SymbiFlow interchange format

  byuccl/spydrnet#143 · Filter by author wirthlin opened on Jun 7, 2021

• Clean up the namespace managers' implementations

  byuccl/spydrnet#142 · Filter by author thunder-hammer opened on Jun 2, 2021
  2

  

• Verilog Parser features required to parse Quartus Prime .vo/vqm files

  byuccl/spydrnet#141 · Filter by author thunder-hammer opened on May 25, 2021
  4

  

• Analyze and improve constant support Verilog Parser

  byuccl/spydrnet#140 · Filter by author thunder-hammer opened on May 25, 2021

• instance.get_pins() vs instance.pins

  major
  byuccl/spydrnet#139 · Filter by author jacobdbrown4 opened on May 24, 2021
  6

• Documentation about building the documentation

  byuccl/spydrnet#138 · Filter by author thunder-hammer opened on May 24, 2021

• Need to document the examples

  good first issue
  byuccl/spydrnet#136 · Filter by author wirthlin opened on May 17, 2021
  1