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ad9088: Series of fixes to enable ADI_APOLLO_NCO_CHAN_SEL_DIRECT_GPIO #3466

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ad9088: Series of fixes to enable ADI_APOLLO_NCO_CHAN_SEL_DIRECT_GPIO #3466

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c9e9202
iio: trx-rf: ad9088: Fix property length
gastmaier Jul 28, 2026
f50e73a
iio: trx-rf: ad9088: Fix redundant negative check
gastmaier Jul 28, 2026
dbf58d3
dt-bindings: iio: adc: ad9088: adi,gpio-quick-config
gastmaier Jul 30, 2026
960a69e
iio: trx-rf: ad9088: Support adi,gpio-quick-config
gastmaier Jul 30, 2026
edd66eb
iio: trx-rf: ad9088: API, fix IDX_NONE check
gastmaier Jul 30, 2026
fc05f0e
iio: trx-rf: ad9088: Fix ad9088_read_gpio_hop_array() return
gastmaier Aug 5, 2026
54bf970
iio: trx-rf: ad9088: Fix _ad9088_ffh sizes
gastmaier Aug 5, 2026
d199528
iio: trx-rf: ad9088: Fix FNCO hop-enable mask
gastmaier Aug 5, 2026
29d922e
iio: trx-rf: ad9088: Fix FNCO restore-state index
gastmaier Aug 5, 2026
6b9f619
iio: trx-rf: ad9088: Fix FFH FNCO printf
gastmaier Aug 5, 2026
5cb216d
iio: trx-rf: ad9088: Fix RX FNCO hop enable
gastmaier Aug 5, 2026
a820388
iio: trx-rf: ad9088: Fix FFH indexing
gastmaier Aug 5, 2026
f57b1f6
iio: trx-rf: ad9088: Program full FNCO/CNCO hop
gastmaier Aug 5, 2026
60d0366
iio: trx-rf: ad9088: Ensure symmetry in ffh modes
gastmaier Aug 5, 2026
0d675d7
iio: trx-rf: ad9088: Use ad9088_check_apollo_error()
gastmaier Aug 5, 2026
35c32a6
ad9084: vck190: dts: GPIO FFH w/ profile_fcn_sel[3]@15
gastmaier Jul 30, 2026
7155e2f
ad9084: vpk180: dts: GPIO FFH w/ profile_fcn_sel[3]@15
gastmaier Jul 30, 2026
61e9c1d
iio: trx-rf: ad9088: API: Wrong parameter orders
gastmaier Aug 7, 2026
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9 changes: 9 additions & 0 deletions Documentation/devicetree/bindings/iio/trx-rf/adi,ad9088.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -129,6 +129,15 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
description: JESD subclass setting.

adi,gpio-quick-config:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 8
description:
GPIO quick configuration profile to apply, indexed from 1 to 8. Explicit
GPIO mappings override the quick configuration mapped pins. Value 0 does
not set any preset, fully relying on the explicit GPIO mappings.

adi,gpio-hop-profile:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
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12 changes: 8 additions & 4 deletions arch/arm64/boot/dts/xilinx/versal-vck190-reva-ad9084.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -65,12 +65,12 @@

/ {
clocks {
clkin_125: clock@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_125";
};

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(unit_address_vs_reg): /clocks/clock@0: node has a unit name, but no reg or ranges property

ref_clk {
#clock-cells = <0>;
Expand Down Expand Up @@ -209,34 +209,34 @@
#size-cells = <0x1>;
ranges = <0 0 0 0xffffffff>;

clocks {
rx_fixed_linerate: clock@1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <AD9084_RX_LANERATE_KHZ>;
clock-output-names = "rx_lane_clk";
};

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(unit_address_vs_reg): /fpga-axi@0/clocks/clock@1: node has a unit name, but no reg or ranges property

tx_fixed_linerate: clock@2 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <AD9084_TX_LANERATE_KHZ>;
clock-output-names = "tx_lane_clk";
};

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(unit_address_vs_reg): /fpga-axi@0/clocks/clock@2: node has a unit name, but no reg or ranges property

rx_fixed_link_clk: clock@3 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <AD9084_RX_LINK_CLK>;
clock-output-names = "rx_link_clk";
};

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(unit_address_vs_reg): /fpga-axi@0/clocks/clock@3: node has a unit name, but no reg or ranges property

tx_fixed_link_clk: clock@4 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <AD9084_TX_LINK_CLK>;
clock-output-names = "tx_link_clk";
};

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(unit_address_vs_reg): /fpga-axi@0/clocks/clock@4: node has a unit name, but no reg or ranges property
};

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(simple_bus_reg): /fpga-axi@0/clocks: missing or empty reg/ranges property

axi_gpio: gpio@a4000000 {
Expand Down Expand Up @@ -749,9 +749,13 @@

// adi,cddc-bmem-sample-delay-en;
// adi,fddc-bmem-sample-delay-en;

/* GPIO frequency hopping configuration (optional) */
//adi,gpio-hop-profile = <19 20 21 22 23>;
//adi,gpio-hop-block = <15 16 17 18>;
adi,gpio-quick-config = <1>; // ADI_APOLLO_QUICK_CFG_PROFILE_1

/* GPIO frequency hopping configuration (axi_gpio offset +15) */
adi,gpio-hop-terminal = <17 18>;
adi,gpio-hop-slice = <19 20 21>;
adi,gpio-hop-side = <22>;
adi,gpio-hop-block = <23 24 25 15>;
adi,gpio-hop-profile = <26 27 28 29 30>;
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};
};
9 changes: 9 additions & 0 deletions arch/arm64/boot/dts/xilinx/versal-vpk180-reva-ad9084.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -174,13 +174,13 @@
#size-cells = <0x1>;
ranges = <0 0 0 0xffffffff>;

clocks {
rx_fixed_linerate: clock@1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <AD9084_RX_LANERATE_KHZ>;
clock-output-names = "rx_lane_clk";
};

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(unit_address_vs_reg): /fpga-axi@0/clocks/clock@1: node has a unit name, but no reg or ranges property

tx_fixed_linerate: clock@2 {
#clock-cells = <0>;
Expand Down Expand Up @@ -685,5 +685,14 @@
adi,subclass = <JESD_SUBCLASS>;

adi,invalid-en;

adi,gpio-quick-config = <1>; // ADI_APOLLO_QUICK_CFG_PROFILE_1

/* GPIO frequency hopping configuration (axi_gpio offset +15) */
adi,gpio-hop-terminal = <17 18>;
adi,gpio-hop-slice = <19 20 21>;
adi,gpio-hop-side = <22>;
adi,gpio-hop-block = <23 24 25 15>;
adi,gpio-hop-profile = <26 27 28 29 30>;
};
};
18 changes: 9 additions & 9 deletions drivers/iio/trx-rf/ad9088/ad9088.h
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Original file line number Diff line number Diff line change
Expand Up @@ -153,17 +153,17 @@ struct ad9088_clock {

struct _ad9088_ffh {
struct {
u8 index[ADI_APOLLO_NUM_SIDES * ADI_APOLLO_FNCO_NUM];
u64 frequency[ADI_APOLLO_FNCO_PROFILE_NUM];
u8 select[ADI_APOLLO_NUM_SIDES * ADI_APOLLO_FNCO_NUM];
bool en[ADI_APOLLO_NUM_SIDES * ADI_APOLLO_FNCO_NUM];
u8 mode[ADI_APOLLO_FNCO_PROFILE_NUM];
u8 index[ADI_APOLLO_FNCO_NUM];
u64 frequency[ADI_APOLLO_FNCO_NUM][ADI_APOLLO_FNCO_PROFILE_NUM];

@nunojsa nunojsa Aug 7, 2026

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Hmm I guess this change makes the series non bisectable? So, ideally every commit should remain in a working state (of course to best of our knowledge) and compile. The working state sometimes is harder but being compile is a must.

So couple all the data changes with the code path that actually depend on it. If you think it still makes sense to have separate patches per field (index, frequency, etc...) fine. Or by logical change...

u8 select[ADI_APOLLO_FNCO_NUM];
bool en[ADI_APOLLO_FNCO_NUM];
u8 mode[ADI_APOLLO_FNCO_NUM];
} fnco;
struct {
u8 index[ADI_APOLLO_NUM_SIDES * ADI_APOLLO_CNCO_NUM];
u64 frequency[ADI_APOLLO_CNCO_PROFILE_NUM];
u8 select[ADI_APOLLO_NUM_SIDES * ADI_APOLLO_CNCO_NUM];
u8 mode[ADI_APOLLO_CNCO_PROFILE_NUM];
u8 index[ADI_APOLLO_CNCO_NUM];
u64 frequency[ADI_APOLLO_CNCO_NUM][ADI_APOLLO_CNCO_PROFILE_NUM];
u8 select[ADI_APOLLO_CNCO_NUM];
u8 mode[ADI_APOLLO_CNCO_NUM];
} cnco;
};

Expand Down
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