I am an Electronics and Communication Engineering student with a dedicated focus on VLSI, digital logic design, and practical hardware implementation. My core objective is to bridge theoretical electronic concepts with physical engineering, from writing Verilog for complex RTL designs to routing custom printed circuit boards.
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RV32I 32-bit Single-Cycle RISC-V Processor
Designed and implemented a 32-bit single-cycle RISC-V processor (RV32I) in SystemVerilog with a modular Harvard architecture. The processor was functionally verified using ModelSim and Xilinx Vivado Simulator, and successfully synthesized targeting the Digilent Basys 3 (Artix-7) FPGA. Developed and executed benchmark programs including Fibonacci Series, Bubble Sort, Maximum Value in an Array, and Student Grading. Also designed a custom Instruction Set Extension (ISE) to accelerate the grading benchmark, reducing execution from approximately 600 clock cycles to around 400 clock cycles.
VLSI & Digital Design
Implementing digital logic systems, including an 8-bit Arithmetic Logic Unit (ALU), using Verilog HDL and Xilinx Vivado. Actively exploring the open-source RTL-to-GDSII flow.
Custom Hardware Engineering
Designing and assembling a custom ATmega328P development board, managing the complete pipeline from schematics and BOM creation to SMD soldering.
Low-Level Programming
Developing a collection of Arduino-based mini-projects to strengthen my understanding of embedded systems, sensors, actuators, and display modules. Utilizing C and Python for bare-metal programming and hardware interfacing.
Hardware Description & Programming: