MCPU-Compiler

Note

This project is currently in active development and is not yet feature-complete. A major project restructure is currently in progress. For the most up-to-date features, please switch to the dev branch.

The MCPU Compiler implements a multi-stage pipeline designed for architectural flexibility. It compiles a C-inspired language into "mcode", a custom intermediate representation that abstracts away hardware-specific constraints. Designed with a modular foundation, the project decouples the high-level logic from the physical instruction set. This allows developers to either use the built-in assembler targeting the MCPU architecture or implement their own backends to target custom hardware.

Language Reference

Note

As previously stated, this project is in active development. The syntax and core behavior of the language are subject to change.

The currently unnamed language is an explicit, statically-typed, procedural language. While the compiler handles most memory operations implicitly, it provides optional low-level primitives such as direct pointer manipulation and manual memory deallocation.

Variables & Types

The language supports standard primitives as either scalars or arrays. Arrays are fixed-size and can be initialized with literals or existing variables.

Primitive Types: int, bool

int x = 5;
bool active = true;

int[] arr = [1, 2, x];                // Integer array initialization
bool[] b_arr = [true, false, active]; // Boolean array initialization

int[3] arr;                           // Empty integer array initialization

Low-Level Control & I/O

Supports direct hardware and memory access through specialized primitives.

Pointers & Memory

Supports pointer logic with zero runtime overhead. Pointers are resolved at compile time and do not occupy additional memory in the final binary.

• Reference (&): Retrieves the address of a variable.
• Dereference (^): Accesses the value at a pointer's address.
• Manual Deallocation: The free() statement is provided.

int x = 1;
*int px = &x;  // Define pointer using *type; assign address using &
int y = ^px;   // Dereference using ^

free(x);       // Manually unload x from memory

Hardware I/O

The io keyword provides direct communication with a system's I/O.

• io in: Reads an integer from the input stream.
• io out: Outputs a value of any type to the output stream

int input;
io in input;   // Accept integer input

int y = input + 5;
io out y;      // Output value of y

Control Flow

Supports standard procedural control structures.

// Conditional
if (x > 10) { 
  // Logic
}

// For Loop
for (int i = 1; i < 3; i++;) {
  // Logic
}

// While Loop
while (condition == false) {
  // Logic
}

Functions

Supports standard function declarations and calls. Unlike C, functions are non-linear and can be defined anywhere in a source file regardless of the order of execution. A function's scope is strictly isolated. A function does not inherit or have access to the global scope; all necessary data must be explicitly passed in via parameters.

bool boolean = isOne(y); // Called before definition

bool isOne(int i) {
  return (i == 1);
}

// Recursive function example
int supportsRecursion(n) {
  if (n <= 1) { 
    return n;
  } else {
    return supportsRecursion(n-1) + supportsRecursion(n-2);
  }
}

mcode ISA

Note

As previously stated, this project is in active development. This ISA is subject to expansion.

The mcode ISA serves as the intermediate language of the MCPU Compiler. It was designed with RISC principles in mind, prioritizing a small, highly efficient set of instructions that can be easily mapped to physical hardware backends.

Core Instructions

Mnemonic	Name	Pseudocode	Notes
HLT	Halt	Stop Execution	Terminates program
ADD	Addition	S + T -> D
SUB	Subtraction	S - T -> D
NOR	Bitwise NOR	!(S | T) -> D
AND	Bitwise AND	S & T -> D
XOR	Bitwise XOR	S ^ T -> D
RSH	Right Shift	S >> 1 -> D
LDI	Load Immediate	Imm -> D	Loads a constant into a destination register
ADI	Add Immediate	A + Imm -> A	Adds a constant to a register
JMP	Jump	Addr -> PC
BRH	Branch	If cond: Addr -> PC	Conditional branch based on flags
CAL	Call	Addr -> PC	Pushes PC+1 to stack for function calls
RET	Return	Stack -> PC	Pops address from stack to return from call
LOD	Memory Load	Mem[P + offset] -> D
STR	Memory Store	S -> Mem[P + offset]
IO	Input/Output	I/O <-> Register	Communication with external pins/peripherals

Pseudo-Instructions

Mnemonic	Name	Base Instruction
NOP	No Operation	RSH r0, r0
INC	Increment	ADI 1, rd
DEC	Decrement	ADI 255, rd
CMP	Compare	SUB rs, rt, r0 (Sets flags only)
SBI	Sub Immediate	ADI -(Imm), rd
NEG	Negate	SUB r0, rd, rd
NOT	Bitwise NOT	NOR rd, rd, rd
OR,	Bitwise OR	NOR rs, rt, rd then NOT rd
MOV	Move	ADD r0, rs, rd
CLR	Clear	SUB rd, rd, rd
TST	Test	CMP rs, r0
LDA	Absolute Load	LOD r0, Imm, rd
STA	Absolute Store	STR r0, Imm, rs