This is a proposal for a performance improvement in the D-cache at the cost of extra logic resources.
At present, the D-cache fetches a line on a read-miss or a write-miss. This means that a line is fetched even when it is only written to, increasing the bandwidth requirements of the application. If we had a byte-enable bit for each byte in a cache line, we'd only need to fetch a line on a read-miss, not on a write-miss. These byte-enable bits would increase storage requirements in the cache and also widen the DRAM request token and hence all interconnect carrying DRAM requests.
This is a proposal for a performance improvement in the D-cache at the cost of extra logic resources.
At present, the D-cache fetches a line on a read-miss or a write-miss. This means that a line is fetched even when it is only written to, increasing the bandwidth requirements of the application. If we had a byte-enable bit for each byte in a cache line, we'd only need to fetch a line on a read-miss, not on a write-miss. These byte-enable bits would increase storage requirements in the cache and also widen the DRAM request token and hence all interconnect carrying DRAM requests.