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Precision-Floating-Point-Adder-using-System-Verilog
Precision-Floating-Point-Adder-using-System-Verilog PublicSimulated and Synthesised an adder for the shortened (16-bit) version of the 32-bit IEEE 754 single-precision floating-point format using a State Machine.
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Application-Specific-Embedded-Processor-using-System-Verilog
Application-Specific-Embedded-Processor-using-System-Verilog PublicImplemented a picoMIPS implementation for 1-dimensional Gaussian Smoothing utilising a small number of the FPGA resources, minimising design cost.
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ROBDD-Reachability-Engine
ROBDD-Reachability-Engine PublicA C++ Reduced Ordered Binary Decision Diagram (ROBDD) package utilizing custom hash tables and computed caches for high-performance boolean logic manipulation. Includes a Symbolic Traversal engine …
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Galois-Field-Multiplier
Galois-Field-Multiplier PublicA synchronous SystemVerilog implementation of a GF(2^3) finite field multiplier for cryptographic hardware applications, featuring modular reduction and protection against timing-based side-channel…
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