Fix rssi timeout

.gitattributes

@@ -0,0 +1,4 @@
+* text=auto
+*.c  text eol=lf
+*.h  text eol=lf
+

.github/workflows/build-firmware.yaml

@@ -0,0 +1,25 @@
+name: Build firmware
+
+on:
+  push:
+    branches: [ "*" ]
+
+jobs:
+  build-firmware:
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v4
+      with:
+        fetch-depth: 20
+    - name: Install dependencies
+      run: |
+        sudo apt update && sudo apt install -y sdcc build-essential
+    - name: Build
+      run: |
+        make -C Firmware/ all install
+    - name: Archive build artifacts
+      uses: actions/upload-artifact@v4
+      with:
+        name: firmware
+        path: |
+          Firmware/dst/*

.github/workflows/release.yaml

@@ -0,0 +1,36 @@
+name: Release
+
+on:
+  release:
+    types:
+      - published
+    permissions:
+      contents: write
+
+jobs:
+  build-firmware:
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v4
+    - name: Install dependencies
+      run: |
+        sudo apt update && sudo apt install -y sdcc build-essential zip
+    - name: Build
+      run: |
+        make -C Firmware/ all install
+    - name: Compress
+      run: |
+        mkdir -p $ARCHIVE
+        cp Firmware/dst/* $ARCHIVE/
+        zip -o $ARCHIVE.zip -r $ARCHIVE/
+      env:
+        ARCHIVE: SiK-Firmware-${{ github.event.release.tag_name }}
+    - name: Upload
+      uses: actions/upload-release-asset@v1.0.1
+      env:
+        GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+      with:
+        upload_url: ${{ github.event.release.upload_url }}
+        asset_path: SiK-Firmware-${{ github.event.release.tag_name }}.zip
+        asset_name: SiK-Firmware-${{ github.event.release.tag_name }}.zip
+        asset_content_type: binary/octet-stream

.github/workflows/test_build.yml

@@ -7,7 +7,7 @@ jobs:
     runs-on: ubuntu-22.04
     steps:
       # git checkout the PR
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
 
       - name: Install sdcc
         run: |
@@ -20,7 +20,7 @@ jobs:
           tests/test_build.sh
 
       - name: Archive build binaries
-        uses: actions/upload-artifact@v3
+        uses: actions/upload-artifact@v4
         with:
           name: SiK build
           path: |

Firmware/bootloader/flash.c

@@ -278,7 +278,7 @@ __at(FLASH_CALIBRATION_AREA_HIGH) uint8_t __code calibration[FLASH_CALIBRATION_A
 __at(FLASH_CALIBRATION_CRC_HIGH)	uint8_t __code calibration_crc;
 
 void
-flash_transfer_calibration()
+flash_transfer_calibration(void)
 {
 	uint8_t idx, crc = 0;
 
@@ -318,7 +318,7 @@ flash_transfer_calibration()
 #if defined BOARD_mro900
 static __at(FLASH_CALIBRATION_OSC_HIGH) uint8_t __code calibration;
 
-void flash_transfer_calibration()
+void flash_transfer_calibration(void)
 {
 	if (flash_read_byte(FLASH_CALIBRATION_OSC) != 0xFF)
 	{

Firmware/bootloader/flash.h

@@ -92,7 +92,7 @@ void	flash_write_byte(uint16_t address, uint8_t c);
 uint8_t	flash_read_byte(uint16_t address);
 #endif // FLASH_BANKS
 #if defined BOARD_rfd900a || defined BOARD_rfd900p || defined BOARD_mro900
-void flash_transfer_calibration();
+void flash_transfer_calibration(void);
 #endif
 
 #endif // _FLASH_H_

Firmware/include/board.h

@@ -122,6 +122,10 @@
 # include "board_mro900.h"
 #elif defined(BOARD_3dr1060)
 # include "board_3dr1060.h"
+#elif defined(BOARD_tfsik01_26MHz)
+# include "board_tfsik01_26MHz.h"
+#elif defined(BOARD_tfsik01_30MHz)
+# include "board_tfsik01_30MHz.h"
 #else
 # error Must define a BOARD_ value before including this file.
 #endif

Firmware/include/board_3dr1060.h

@@ -1,6 +1,6 @@
 // -*- Mode: C; c-basic-offset: 8; -*-
 //
-// Copyright (c) 2011 Michael Smith, All Rights Reserved
+// Copyright (c) 2022 ThunderFly s.r.o., All Rights Reserved
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
@@ -93,7 +93,9 @@ SBIT(PIN_ENABLE,   SFR_P0, 3);
 SBIT(NSS1, SFR_SPI1CN, 2); // SI106x Internal Connection
 SBIT(SDN,  SFR_P0, 7);
 
-#define GPIO_0_CONFIG 33 // RX_STATE
-#define GPIO_1_CONFIG 32 // TX_STATE
+#define GPIO_0_CONFIG GPIO_RX_STATE
+#define GPIO_1_CONFIG GPIO_TX_STATE
+#define GPIO_2_CONFIG GPIO_CTS
+#define GPIO_3_CONFIG GPIO_RX_STATE
 
 #endif // _BOARD_3DR1060_H

Firmware/include/board_hb1060.h

@@ -1,6 +1,6 @@
 // -*- Mode: C; c-basic-offset: 8; -*-
 //
-// Copyright (c) 2011 Michael Smith, All Rights Reserved
+// Copyright (c) 2022 ThunderFly s.r.o., All Rights Reserved
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
@@ -46,7 +46,7 @@
 #define CPU_SI1060
 
 #define BOARD_MINTXPOWER 0		// Minimum transmit power level
-#define BOARD_MAXTXPOWER 0x7f	// Maximum transmit power level
+#define BOARD_MAXTXPOWER 20		// Maximum transmit power level
 
 // GPIO definitions (not exported)
 SBIT(LED_RED,	   SFR_P1, 4);
@@ -74,6 +74,9 @@ SBIT(PIN_ENABLE,   SFR_P0, 3);
 	do {							\
 		/* GPIO config */			\
 		P0SKIP	|= 0x0E; /* input pins & nIRQ */ \
+		P0MDOUT |= 0x04; /* CTS pushpull */     \
+		P0MDOUT &= ~0x08; /* RTS open drain */  \
+		P0DRV   &= ~0x04; /* CTS low drive */   \
 		P1SKIP  |= 0x30; /* LEDs */ 			\
 		P0MDOUT |= 0x80; /* radio SDN */		\
 		P1MDOUT |= 0x3D; /* LEDs & radio SPI */ \
@@ -87,13 +90,22 @@ SBIT(PIN_ENABLE,   SFR_P0, 3);
 		IT0	= 0;	/* INT0 level triggered */	\
 	} while(0)
 
+// application/board-specific hardware config
+#define HW_INIT_APPLICATION					\
+	do {							\
+		SFRPAGE	 =  CONFIG_PAGE;			\
+		P0DRV	|=  0x04;		/* CTS */	\
+		SFRPAGE	 =  LEGACY_PAGE;			\
+	} while(0)
 
 #define EZRADIOPRO_OSC_CAP_VALUE 100
 
 SBIT(NSS1, SFR_SPI1CN, 2); // SI106x Internal Connection
 SBIT(SDN,  SFR_P0, 7);
 
-#define GPIO_0_CONFIG 33 // RX_STATE
-#define GPIO_1_CONFIG 32 // TX_STATE
+#define GPIO_0_CONFIG GPIO_RX_STATE
+#define GPIO_1_CONFIG GPIO_TX_STATE
+#define GPIO_2_CONFIG GPIO_CTS
+#define GPIO_3_CONFIG GPIO_RX_STATE
 
 #endif // _BOARD_HB1060_H

Firmware/include/board_ism01a.h

@@ -1,6 +1,6 @@
 // -*- Mode: C; c-basic-offset: 8; -*-
 //
-// Copyright (c) 2011 Michael Smith, All Rights Reserved
+// Copyright (c) 2022 ThunderFly s.r.o., All Rights Reserved
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
@@ -27,13 +27,10 @@
 //
 
 ///
-/// @file	board_rf50.h
+/// @file	board_ism01a.h
 ///
-/// Board-specific definitions for the RF50-DEMO board.
+/// Board-specific definitions for the ISM01A board.
 ///
-
-/// @file	board.h
-///		Board definitions for the ISM01A board
 
 #ifndef _BOARD_ISM01A_H
 #define _BOARD_ISM01A_H
@@ -46,14 +43,18 @@
 #define CPU_SI1060
 
 #define BOARD_MINTXPOWER 0		// Minimum transmit power level
-#define BOARD_MAXTXPOWER 0x7f	// Maximum transmit power level
+#define BOARD_MAXTXPOWER 20		// Maximum transmit power level
 
 // GPIO definitions (not exported)
 SBIT(LED_RED,	   SFR_P1, 4);
 SBIT(LED_GREEN,	   SFR_P1, 5);
 SBIT(PIN_CONFIG,   SFR_P0, 2);
 SBIT(PIN_ENABLE,   SFR_P0, 3);
 
+// Serial flow control
+#define SERIAL_RTS	PIN_ENABLE	// always an input
+#define SERIAL_CTS	PIN_CONFIG	// input in bootloader, output in app
+
 // Signal polarity definitions
 #define LED_ON		1
 #define LED_OFF		0
@@ -70,6 +71,9 @@ SBIT(PIN_ENABLE,   SFR_P0, 3);
 	do {							\
 		/* GPIO config */			\
 		P0SKIP	|= 0x0E; /* input pins & nIRQ */ \
+		P0MDOUT |= 0x04; /* CTS pushpull */     \
+		P0MDOUT &= ~0x08; /* RTS open drain */  \
+		P0DRV   &= ~0x04; /* CTS low drive */   \
 		P1SKIP  |= 0x30; /* LEDs */ 			\
 		P0MDOUT |= 0x80; /* radio SDN */		\
 		P1MDOUT |= 0x3D; /* LEDs & radio SPI */ \
@@ -83,13 +87,22 @@ SBIT(PIN_ENABLE,   SFR_P0, 3);
 		IT0	= 0;	/* INT0 level triggered */	\
 	} while(0)
 
+// application/board-specific hardware config
+#define HW_INIT_APPLICATION					\
+	do {							\
+		SFRPAGE	 =  CONFIG_PAGE;			\
+		P0DRV	|=  0x04;		/* CTS */	\
+		SFRPAGE	 =  LEGACY_PAGE;			\
+	} while(0)
 
 #define EZRADIOPRO_OSC_CAP_VALUE 100
 
 SBIT(NSS1, SFR_SPI1CN, 2); // SI106x Internal Connection
 SBIT(SDN,  SFR_P0, 7);
 
-#define GPIO_0_CONFIG 32 // TX_STATE
-#define GPIO_1_CONFIG 35 // TX_FIFO_EMPTY
+#define GPIO_0_CONFIG ant1
+#define GPIO_1_CONFIG ant2
+#define GPIO_2_CONFIG GPIO_RX_STATE
+#define GPIO_3_CONFIG GPIO_TX_STATE
 
 #endif // _BOARD_ISM01A_H

Firmware/include/board_tfsik01_26MHz.h

@@ -0,0 +1,112 @@
+// -*- Mode: C; c-basic-offset: 8; -*-
+//
+// Copyright (c) 2022 ThunderFly s.r.o., All Rights Reserved
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+//  o Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//  o Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in
+//    the documentation and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+// INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+// OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+
+///
+/// @file       board_tfsik01_26MHz.h
+///
+/// Board-specific definitions for the TFSIK01 hardware fitted with a 26 MHz crystal.
+///
+
+#ifndef _BOARD_TFSIK01_26MHZ_H
+#define _BOARD_TFSIK01_26MHZ_H
+
+#include <compiler_defs.h>
+#include <Si1060_defs.h>
+
+#define BOARD_ID        0x53
+#define BOARD_NAME      "TFSIK01 26MHz"
+#define CPU_SI1060
+
+#define BOARD_MINTXPOWER 0              // Minimum transmit power level
+#define BOARD_MAXTXPOWER 20             // Maximum transmit power level
+
+#define XO_FREQ         26000000UL
+
+// GPIO definitions (not exported)
+SBIT(LED_RED,      SFR_P1, 4);
+SBIT(LED_GREEN,    SFR_P1, 5);
+SBIT(LED_ORANGE,   SFR_P1, 6);
+SBIT(PIN_CONFIG,   SFR_P0, 2);
+SBIT(PIN_ENABLE,   SFR_P0, 3);
+
+// Serial flow control
+#define SERIAL_RTS      PIN_ENABLE      // always an input
+#define SERIAL_CTS      PIN_CONFIG      // input in bootloader, output in app
+
+// Signal polarity definitions
+#define LED_ON          1
+#define LED_OFF         0
+#define BUTTON_ACTIVE   0
+
+// UI definitions
+#define LED_BOOTLOADER  LED_RED
+#define LED_RADIO               LED_GREEN
+#define LED_ACTIVITY    LED_RED
+#define LED_DIVERSITY   LED_ORANGE
+#define BUTTON_BOOTLOAD PIN_CONFIG
+
+// board-specific hardware config
+#define HW_INIT                                         \
+        do {                                                    \
+                /* GPIO config */                       \
+                P0SKIP  |= 0x0E; /* input pins & nIRQ */ \
+                P0MDOUT |= 0x04; /* CTS pushpull */     \
+                P0MDOUT &= ~0x08; /* RTS open drain */  \
+                P0DRV   &= ~0x04; /* CTS low drive */   \
+                P1SKIP  |= 0x30; /* LEDs */                     \
+                P0MDOUT |= 0x80; /* radio SDN */                \
+                P1MDOUT |= 0x3D; /* LEDs & radio SPI */ \
+                                                                \
+                SFRPAGE  = CONFIG_PAGE;                         \
+                P1DRV   |= 0x0D;                                \
+                SFRPAGE  = LEGACY_PAGE;                         \
+                                                                \
+                /* INT0 is the radio interrupt, on P0.1 */ \
+                IT01CF = 0x01; /* active low, P0.1 */   \
+                IT0     = 0;    /* INT0 level triggered */      \
+        } while(0)
+
+// application/board-specific hardware config
+#define HW_INIT_APPLICATION                                     \
+        do {                                                    \
+                SFRPAGE  =  CONFIG_PAGE;                        \
+                P0DRV   |=  0x04;               /* CTS */       \
+                SFRPAGE  =  LEGACY_PAGE;                        \
+        } while(0)
+
+#define EZRADIOPRO_OSC_CAP_VALUE 100
+
+SBIT(NSS1, SFR_SPI1CN, 2); // SI106x Internal Connection
+SBIT(SDN,  SFR_P0, 7);
+
+#define GPIO_0_CONFIG ant1
+#define GPIO_1_CONFIG GPIO_TX_STATE
+#define GPIO_2_CONFIG GPIO_TX_STATE
+#define GPIO_3_CONFIG ant2
+
+#endif // _BOARD_TFSIK01_26MHZ_H