Added LTspice-mode synthesis for L instance Rser, Lser, Rpar, RLshunt, and Cpar

Author: marcin-golebiowski

README.md

@@ -133,6 +133,7 @@ LTspice mode covers syntax such as:
 - model parameter aliases: resistor and capacitor models accept `tc=<tc1>[,<tc2>]`; voltage switches accept `von` / `voff`; current switches accept `ion` / `ioff`
 - resistor instance parasitics `Rser`, `Rpar`, and `Cpar`
 - capacitor instance parasitics `Rser`, `Lser`, `Rpar`, and `Cpar`
+- inductor instance parasitics `Rser`, `Lser`, `Rpar`, `RLshunt`, and `Cpar`
 
 Topology-changing LTspice options that can be represented safely are synthesized as helper components in the parser. Behavior-changing constructs that are not represented by SpiceSharp are reported with targeted diagnostics instead of being silently ignored.
 

roadmap/ltspice-compatibility-matrix.md

@@ -1,8 +1,8 @@
 ---
 title: LTspice Compatibility Matrix
-status: P3 Baseline + .FOUR Support Refresh + Custom Passives + Ideal Diodes + Golden Evidence + Include/Lib Path Evidence + Waveform Docs Refresh + PWL Text Variants + Finite SINE + Source/R-C Parasitics
+status: P3 Baseline + .FOUR Support Refresh + Custom Passives + Ideal Diodes + Golden Evidence + Include/Lib Path Evidence + Waveform Docs Refresh + PWL Text Variants + Finite SINE + Source/R-C/L Parasitics
 scope: SpiceSharpParser + SpiceSharp
-last_reviewed: 2026-07-06
+last_reviewed: 2026-07-07
 ---
 
 # LTspice Compatibility Matrix
@@ -65,7 +65,7 @@ Compatibility classes:
 | LTspice metadata/rating parameters `mfg`, `manufacturer`, `pn`, `part`, `desc`, `description`, `V`, `Irms`, `Ipk` | Accepted | Warning no-op in LTspice mode | No runtime effect | Diagnostic fixture | Default: existing parameter error. LTspice: warning names parameter. | Current parser/runtime | BOM/layout metadata is not used by SpiceSharpParser. |
 | Resistor instance parasitics `Rser`, `Rpar`, `Cpar` | Accepted in LTspice mode | Synthesizes helper R/C entities | OP/TRAN supported | Analytic fixture | None expected for supported forms | Current parser/runtime | Parser-only topology synthesis: `Rser` adds a series resistor through an internal node; `Rpar` and `Cpar` add shunts across the resistor terminals. Core resistor model is unchanged. |
 | Capacitor instance parasitics `Rser`, `Lser`, `Rpar`, `Cpar` | Accepted in LTspice mode | Synthesizes helper R/L/C entities | OP/TRAN supported for R helpers and `Cpar`; `Lser` read fixture | Analytic/parser fixture | None expected for supported forms | Current parser/runtime | Parser-only topology synthesis: `Rser` and `Lser` add a series chain through internal nodes; `Rpar` and `Cpar` add shunts across the capacitor terminals. Core capacitor model is unchanged. |
-| Remaining inductor instance parasitics `Rser`, `Rpar`, `Cpar`, `Lser`, `RLshunt` | Accepted | Rejected in LTspice mode | Not runnable | None | Targeted LTspice instance-parameter error names parameter | Current parser/runtime | Topology-changing inductor parasitics are not synthesized yet; resistor/capacitor forms are tracked separately above. |
+| Inductor instance parasitics `Rser`, `Lser`, `Rpar`, `RLshunt`, `Cpar` | Accepted in LTspice mode | Synthesizes helper R/L/C entities | OP/TRAN supported for resistance helpers; `Lser` / `Cpar` read fixtures | Analytic/parser fixture | None expected for supported forms | Current parser/runtime | Parser-only topology synthesis: `Rser` and `Lser` add a series helper chain through internal nodes; `Rpar`, `RLshunt`, and `Cpar` add shunts across the inductor terminals. Core inductor model is unchanged. |
 | Capacitor `Q=<expr>` and inductor `Flux=<expr>` | Accepted | Core LTspice mode: targeted diagnostic. With `UseCustomComponents()`: produces `NonlinearCapacitor` / `NonlinearInductor`. | Custom components: TRAN and AC supported with operating-point incremental capacitance/inductance. | Focused parser/TRAN/AC fixtures plus optional LTspice-backed AC/TRAN golden comparisons | Core LTspice mode still emits targeted charge/flux diagnostic when custom mappings are not enabled | `SpiceSharpParser.CustomComponents` | `Q` uses `x` as terminal voltage and supports `IC`, `M`, and `N`; `Flux` uses `x` as branch current. Optional goldens compare AC small-signal voltage and transient waveform samples against LTspice when `LTSPICE_EXE` is configured. |
 | LTspice ideal diode parameters `Ron`, `Roff`, `Vfwd`, `Vrev`, `Rrev`, `Ilimit`, `RevIlimit`, `Epsilon`, `RevEpsilon` | Accepted | Core LTspice mode: targeted diagnostic. With `UseCustomComponents()`: produces `IdealDiodeModel` / `IdealDiode`. | Custom component: OP/DC/AC/TRAN supported as a memoryless nonlinear conductance. | Focused parser/integration/unit fixtures plus optional LTspice-backed DC sweep, AC, and rectifier-transient golden comparisons | Core LTspice mode still emits targeted ideal-diode diagnostics when custom mappings are not enabled | `SpiceSharpParser.CustomComponents` | These select LTspice's idealized diode behavior, not Berkeley diode parameters. The custom component supports model parameters, instance overrides, `M`/`N` scaling, `OFF`, and L/W model-bin selection; it does not model junction charge, capacitance, semiconductor noise, or temperature physics. |
 | Switch aliases `von`/`voff` and `ion`/`ioff` | Accepted | Lowered to `vt`/`vh` and `it`/`ih` | Existing switch model behavior | Read fixture | Missing pair or mixed native/alias forms are targeted errors | Current parser/runtime | Midpoint and half-span lowering only; no LTspice numeric parity claim. |

roadmap/ltspice-netlist-compatibility-plan.md

@@ -2,7 +2,7 @@
 title: LTspice Netlist Compatibility Plan
 status: Draft / Roadmap
 scope: SpiceSharpParser + SpiceSharp
-last_reviewed: 2026-07-06
+last_reviewed: 2026-07-07
 ---
 
 # LTspice Netlist Compatibility Plan
@@ -42,7 +42,7 @@ This roadmap is intentionally parser-first and evidence-first:
 - MOS model generation currently covers legacy levels 1, 2, and 3. LTspice `VDMOS` and advanced monolithic levels such as BSIM/EKV/HiSIM variants are runtime or intentional-unsupported candidates.
 - Distributed-line support currently starts from lossless `T`. LTspice lossy `O` / `LTRA` and uniform RC-line `URC` models need engine triage before runnable support is claimed.
 - P3 LTspice mode maps R/C model `tc=a[,b]`, switch `von`/`voff`, and current-switch `ion`/`ioff` aliases where they lower to existing parameters.
-- P3 LTspice mode warns on recognized metadata/rating parameters, synthesizes resistor `Rser` / `Rpar` / `Cpar` and capacitor `Rser` / `Lser` / `Rpar` / `Cpar` helper topology, and emits targeted errors for remaining topology-changing passive parasitics, ideal-diode parameters when custom mappings are not enabled, switch current-limiting/series options, `VDMOS`, high MOS levels, three-terminal power-MOS syntax, and `O` / `LTRA` / `U` / `URC` line families. The optional custom component package adds runnable `IdealDiode` support for LTspice-style diode parameters plus `NonlinearCapacitor` / `NonlinearInductor` support for LTspice-style capacitor `Q=` and inductor `Flux=` forms when `UseCustomComponents()` is enabled, with optional LTspice-backed DC/AC/transient golden comparisons when `LTSPICE_EXE` is configured.
+- P3 LTspice mode warns on recognized metadata/rating parameters, synthesizes resistor `Rser` / `Rpar` / `Cpar`, capacitor `Rser` / `Lser` / `Rpar` / `Cpar`, and inductor `Rser` / `Lser` / `Rpar` / `RLshunt` / `Cpar` helper topology, and emits targeted errors for ideal-diode parameters when custom mappings are not enabled, switch current-limiting/series options, `VDMOS`, high MOS levels, three-terminal power-MOS syntax, and `O` / `LTRA` / `U` / `URC` line families. The optional custom component package adds runnable `IdealDiode` support for LTspice-style diode parameters plus `NonlinearCapacitor` / `NonlinearInductor` support for LTspice-style capacitor `Q=` and inductor `Flux=` forms when `UseCustomComponents()` is enabled, with optional LTspice-backed DC/AC/transient golden comparisons when `LTSPICE_EXE` is configured.
 
 ## Scope And Policy
 
@@ -241,12 +241,13 @@ Implemented P3 behavior:
 - Warned on recognized LTspice metadata and rating parameters only in LTspice mode.
 - Added LTspice-mode parser synthesis for resistor instance parasitics: `Rser` adds a series resistor through an internal node, while `Rpar` and `Cpar` add shunts across the resistor terminals.
 - Added LTspice-mode parser synthesis for capacitor instance parasitics: `Rser` and `Lser` add a series helper chain through internal nodes, while `Rpar` and `Cpar` add shunts across the capacitor terminals.
-- Added targeted diagnostics for remaining topology-changing passive parasitics, LTspice ideal-diode parameters when custom mappings are not enabled, switch `Lser` / `Vser` / `Ilimit`, high MOS levels, `VDMOS`, three-terminal power-MOS syntax, and `O` / `LTRA` / `U` / `URC` line families. LTspice ideal-diode parameters, capacitor `Q=`, and inductor `Flux=` remain targeted diagnostics in core LTspice mode but are runnable through `SpiceSharpParser.CustomComponents` as `IdealDiode`, `NonlinearCapacitor`, and `NonlinearInductor`, with optional LTspice-backed DC/AC/transient golden evidence.
+- Added LTspice-mode parser synthesis for inductor instance parasitics: `Rser` and `Lser` add a series helper chain through internal nodes, while `Rpar`, `RLshunt`, and `Cpar` add shunts across the inductor terminals.
+- Added targeted diagnostics for LTspice ideal-diode parameters when custom mappings are not enabled, switch `Lser` / `Vser` / `Ilimit`, high MOS levels, `VDMOS`, three-terminal power-MOS syntax, and `O` / `LTRA` / `U` / `URC` line families. LTspice ideal-diode parameters, capacitor `Q=`, and inductor `Flux=` remain targeted diagnostics in core LTspice mode but are runnable through `SpiceSharpParser.CustomComponents` as `IdealDiode`, `NonlinearCapacitor`, and `NonlinearInductor`, with optional LTspice-backed DC/AC/transient golden evidence.
 
 Remaining follow-up:
 
 - Broaden model-family alias tables only when direct SpiceSharp equivalents are confirmed by fixtures.
-- Add engine or parser-synthesis work before claiming runnable support for `VDMOS`, advanced MOS families, lossy transmission lines, uniform RC lines, or remaining inductor passive parasitics.
+- Add engine or parser-synthesis work before claiming runnable support for `VDMOS`, advanced MOS families, lossy transmission lines, or uniform RC lines.
 - Keep vendor-library import tests synthetic unless redistribution is clearly permitted.
 
 Initial model-family priorities:

src/SpiceSharpParser.IntegrationTests/LTspiceCompatibility/LTspiceCompatibilityP3Tests.cs

@@ -395,14 +395,183 @@ public void When_LtspiceCapacitorParallelResistanceIsInsideRepeatedSubcircuits_E
             Assert.True(EqualsWithTol(0.75, exports[1]));
         }
 
+        [Fact]
+        public void When_LtspiceInductorSeriesResistanceIsRead_Expect_SynthesizedSeriesResistance()
+        {
+            var model = GetSpiceSharpModelWithCompatibility(
+                CompatibilityOptions.LTspice,
+                "LTspice P3 - inductor Rser",
+                "V1 in 0 1",
+                "L1 in out 1m Rser=10",
+                "RLOAD out 0 90",
+                ".op",
+                ".save V(out)",
+                ".end");
+
+            AssertNoValidationIssues(model.ValidationResult);
+            Assert.True(EqualsWithTol(0.9, RunOpSimulation(model, "V(out)")));
+            Assert.IsType<Resistor>(model.Circuit["L1_rser"]);
+        }
+
+        [Fact]
+        public void When_LtspiceInductorParallelResistanceIsRead_Expect_SynthesizedTransientShunt()
+        {
+            var model = GetSpiceSharpModelWithCompatibility(
+                CompatibilityOptions.LTspice,
+                "LTspice P3 - inductor Rpar",
+                "I1 out 0 PULSE(0 -1m 1n 1n 1n 10u 20u)",
+                "L1 out 0 1m Rpar=1k",
+                ".tran 100n 5u",
+                ".save V(out)",
+                ".end");
+
+            AssertNoValidationIssues(model.ValidationResult);
+            Assert.IsType<Resistor>(model.Circuit["L1_rpar"]);
+
+            var exports = RunTransientSimulation(model, "V(out)");
+            Assert.NotEmpty(exports);
+
+            var oneTau = exports.OrderBy(export => Math.Abs(export.Item1 - 1e-6)).First();
+            Assert.InRange(oneTau.Item2, 0.28, 0.45);
+            Assert.InRange(exports.Last().Item2, -0.02, 0.02);
+        }
+
+        [Fact]
+        public void When_LtspiceInductorRlshuntIsRead_Expect_SynthesizedTransientShunt()
+        {
+            var model = GetSpiceSharpModelWithCompatibility(
+                CompatibilityOptions.LTspice,
+                "LTspice P3 - inductor RLshunt",
+                "I1 out 0 PULSE(0 -1m 1n 1n 1n 10u 20u)",
+                "L1 out 0 1m RLshunt=1k",
+                ".tran 100n 5u",
+                ".save V(out)",
+                ".end");
+
+            AssertNoValidationIssues(model.ValidationResult);
+            Assert.IsType<Resistor>(model.Circuit["L1_rlshunt"]);
+
+            var exports = RunTransientSimulation(model, "V(out)");
+            Assert.NotEmpty(exports);
+
+            var oneTau = exports.OrderBy(export => Math.Abs(export.Item1 - 1e-6)).First();
+            Assert.InRange(oneTau.Item2, 0.28, 0.45);
+            Assert.InRange(exports.Last().Item2, -0.02, 0.02);
+        }
+
+        [Fact]
+        public void When_LtspiceInductorParallelCapacitanceIsRead_Expect_SynthesizedParallelCapacitor()
+        {
+            var model = GetSpiceSharpModelWithCompatibility(
+                CompatibilityOptions.LTspice,
+                "LTspice P3 - inductor Cpar",
+                "L1 out 0 1m Cpar=1n",
+                ".end");
+
+            AssertNoValidationIssues(model.ValidationResult);
+            Assert.IsType<Capacitor>(model.Circuit["L1_cpar"]);
+        }
+
+        [Fact]
+        public void When_LtspiceInductorSeriesInductanceIsRead_Expect_SynthesizedSeriesInductor()
+        {
+            var model = GetSpiceSharpModelWithCompatibility(
+                CompatibilityOptions.LTspice,
+                "LTspice P3 - inductor Lser",
+                "L1 out 0 1m Lser=1u",
+                ".end");
+
+            AssertNoValidationIssues(model.ValidationResult);
+            Assert.IsType<Inductor>(model.Circuit["L1_lser"]);
+        }
+
+        [Fact]
+        public void When_LtspiceInductorHasCombinedParasitics_Expect_AllHelpersAreSynthesized()
+        {
+            var model = GetSpiceSharpModelWithCompatibility(
+                CompatibilityOptions.LTspice,
+                "LTspice P3 - inductor combined parasitics",
+                "L1 out 0 1m Rser=1 Lser=1u Rpar=1k RLshunt=2k Cpar=1n",
+                ".end");
+
+            AssertNoValidationIssues(model.ValidationResult);
+            Assert.IsType<Resistor>(model.Circuit["L1_rser"]);
+            Assert.IsType<Inductor>(model.Circuit["L1_lser"]);
+            Assert.IsType<Resistor>(model.Circuit["L1_rpar"]);
+            Assert.IsType<Resistor>(model.Circuit["L1_rlshunt"]);
+            Assert.IsType<Capacitor>(model.Circuit["L1_cpar"]);
+        }
+
+        [Fact]
+        public void When_LtspiceInductorParasiticValuesUseParameters_Expect_HelperExpressionsResolve()
+        {
+            var model = GetSpiceSharpModelWithCompatibility(
+                CompatibilityOptions.LTspice,
+                "LTspice P3 - inductor parameterized parasitics",
+                ".param rs=10",
+                ".param ls=1u",
+                ".param rp=1k",
+                ".param rls=2k",
+                ".param cp=1n",
+                "V1 in 0 1",
+                "L1 in out 1m Rser={rs} Lser={ls} Rpar={rp} RLshunt={rls} Cpar={cp}",
+                "RLOAD out 0 90",
+                ".op",
+                ".save V(out)",
+                ".end");
+
+            AssertNoValidationIssues(model.ValidationResult);
+
+            var inToOutResistance = 1.0 / ((1.0 / 10.0) + (1.0 / 1000.0) + (1.0 / 2000.0));
+            var expected = 90.0 / (90.0 + inToOutResistance);
+
+            Assert.True(EqualsWithTol(expected, RunOpSimulation(model, "V(out)")));
+            Assert.IsType<Resistor>(model.Circuit["L1_rser"]);
+            Assert.IsType<Inductor>(model.Circuit["L1_lser"]);
+            Assert.IsType<Resistor>(model.Circuit["L1_rpar"]);
+            Assert.IsType<Resistor>(model.Circuit["L1_rlshunt"]);
+            Assert.IsType<Capacitor>(model.Circuit["L1_cpar"]);
+        }
+
+        [Fact]
+        public void When_LtspiceInductorSeriesParasiticIsInsideRepeatedSubcircuits_Expect_InternalNodesAreScoped()
+        {
+            var model = GetSpiceSharpModelWithCompatibility(
+                CompatibilityOptions.LTspice,
+                "LTspice P3 - inductor Rser subcircuit scoping",
+                "V1 in 0 1",
+                "XU1 in out1 lcell",
+                "XU2 in out2 lcell",
+                "RLOAD1 out1 0 90",
+                "RLOAD2 out2 0 40",
+                ".subckt lcell p out",
+                "L1 p out 1m Rser=10",
+                ".ends lcell",
+                ".op",
+                ".save V(out1)",
+                ".save V(out2)",
+                ".end");
+
+            AssertNoValidationIssues(model.ValidationResult);
+
+            var exports = RunOpSimulation(model, "V(out1)", "V(out2)");
+            Assert.True(EqualsWithTol(0.9, exports[0]));
+            Assert.True(EqualsWithTol(0.8, exports[1]));
+        }
+
         [Theory]
         [InlineData("R1 out 0 1k Rser=1", "Rser")]
         [InlineData("R1 out 0 1k Rpar=1Meg", "Rpar")]
         [InlineData("C1 out 0 1n Rser=1", "Rser")]
         [InlineData("C1 out 0 1n Lser=1n", "Lser")]
         [InlineData("C1 out 0 1n Rpar=1k", "Rpar")]
         [InlineData("C1 out 0 1n Cpar=1n", "Cpar")]
-        public void When_ResistorOrCapacitorParasiticIsReadWithoutLtspiceCompatibility_Expect_DefaultError(
+        [InlineData("L1 out 0 1u Rser=1", "Rser")]
+        [InlineData("L1 out 0 1u Lser=1n", "Lser")]
+        [InlineData("L1 out 0 1u Rpar=1k", "Rpar")]
+        [InlineData("L1 out 0 1u RLshunt=1k", "RLshunt")]
+        [InlineData("L1 out 0 1u Cpar=1p", "Cpar")]
+        public void When_PassiveParasiticIsReadWithoutLtspiceCompatibility_Expect_DefaultError(
             string componentLine,
             string parameterName)
         {
@@ -417,10 +586,6 @@ public void When_ResistorOrCapacitorParasiticIsReadWithoutLtspiceCompatibility_E
         }
 
         [Theory]
-        [InlineData("L1 out 0 1u Rser=1", "Rser", "parasitic")]
-        [InlineData("L1 out 0 1u Rpar=1k", "Rpar", "parasitic")]
-        [InlineData("L1 out 0 1u Cpar=1p", "Cpar", "parasitic")]
-        [InlineData("L1 out 0 1u RLshunt=1k", "RLshunt", "parasitic")]
         [InlineData("C1 out 0 Q=1n*x", "Q", "charge-defined")]
         [InlineData("C1 out 0 Q=1n*x Rser=1", "Q", "charge-defined")]
         [InlineData("L1 out 0 Flux=1m*tanh(x)", "Flux", "flux-defined")]