Improve LTspice mode: resistor instance parasitics and capacitor instance parasitics

Author: marcin-golebiowski

README.md

@@ -123,7 +123,18 @@ reader.Settings.Compatibility = CompatibilityOptions.LTspice;
 var model = reader.Read(parseResult.FinalModel);
 ```
 
-LTspice mode covers fixture-backed generated-netlist syntax such as `.backanno` and selected output/viewer options as warning no-ops, one-argument `.TRAN`, scalar expression aliases, finite-cycle `PULSE(... Ncycles)`, `EXP(...)`, independent-source `tbl=(...)`, R/C model `tc=a[,b]`, and switch threshold aliases. Behavior-changing constructs that are not represented by SpiceSharp are reported with targeted diagnostics instead of being silently ignored.
+LTspice mode covers syntax such as:
+
+- `.backanno` and selected output/viewer options as warning no-ops
+- one-argument `.TRAN` with a derived step policy
+- scalar expression aliases and `table(...)` / `tbl(...)`
+- source waveforms including `EXP(...)`, finite-cycle `PULSE(... Ncycles)`, finite-cycle `SINE(... Ncycles)`, and local two-column `PWL file=<path>` data
+- independent-source topology options: `Rser`, `Cpar`, `load`, and `R=<value>`
+- model parameter aliases: resistor and capacitor models accept `tc=<tc1>[,<tc2>]`; voltage switches accept `von` / `voff`; current switches accept `ion` / `ioff`
+- resistor instance parasitics `Rser`, `Rpar`, and `Cpar`
+- capacitor instance parasitics `Rser`, `Lser`, `Rpar`, and `Cpar`
+
+Topology-changing LTspice options that can be represented safely are synthesized as helper components in the parser. Behavior-changing constructs that are not represented by SpiceSharp are reported with targeted diagnostics instead of being silently ignored.
 
 See the [LTspice compatibility matrix](roadmap/ltspice-compatibility-matrix.md) and [LTspice netlist compatibility plan](roadmap/ltspice-netlist-compatibility-plan.md) for the current support classes, known gaps, and evidence policy. LTspice schematic and symbol import (`.asc` / `.asy`) is out of scope.
 

roadmap/ltspice-compatibility-matrix.md

@@ -1,6 +1,6 @@
 ---
 title: LTspice Compatibility Matrix
-status: P3 Baseline + .FOUR Support Refresh + Custom Passives + Ideal Diodes + Golden Evidence + Include/Lib Path Evidence + Waveform Docs Refresh + PWL Text Variants + Finite SINE + Source Parasitics
+status: P3 Baseline + .FOUR Support Refresh + Custom Passives + Ideal Diodes + Golden Evidence + Include/Lib Path Evidence + Waveform Docs Refresh + PWL Text Variants + Finite SINE + Source/R-C Parasitics
 scope: SpiceSharpParser + SpiceSharp
 last_reviewed: 2026-07-06
 ---
@@ -63,7 +63,9 @@ Compatibility classes:
 | Source `Rser`, `Cpar`, `load`, `R=<value>` | Accepted | Synthesizes helper R/C entities in LTspice mode | OP supported for resistance helpers; Cpar read fixture | Analytic/parser fixture | Malformed value forms produce targeted LTspice source-option diagnostics | Current parser/runtime | Parser-only topology synthesis: `Rser` adds a series resistor, `Cpar` adds a shunt capacitor, `load` adds a shunt resistor, and `R=<value>` maps to series resistance on voltage sources and load resistance on current sources. Core source models are unchanged. |
 | R/C model `tc=a[,b]` | Accepted | Lowered to `tc1` / `tc2` | Existing R/C model behavior | Read fixture | None expected in LTspice mode | Current parser/runtime | Parser shim only; coefficients beyond two are rejected. |
 | LTspice metadata/rating parameters `mfg`, `manufacturer`, `pn`, `part`, `desc`, `description`, `V`, `Irms`, `Ipk` | Accepted | Warning no-op in LTspice mode | No runtime effect | Diagnostic fixture | Default: existing parameter error. LTspice: warning names parameter. | Current parser/runtime | BOM/layout metadata is not used by SpiceSharpParser. |
-| R/C/L instance parasitics `Rser`, `Rpar`, `Cpar`, `Lser`, `RLshunt` | Accepted | Rejected in LTspice mode | Not runnable | None | Targeted LTspice instance-parameter error names parameter | Current parser/runtime | Topology-changing passive parasitics are not synthesized. |
+| Resistor instance parasitics `Rser`, `Rpar`, `Cpar` | Accepted in LTspice mode | Synthesizes helper R/C entities | OP/TRAN supported | Analytic fixture | None expected for supported forms | Current parser/runtime | Parser-only topology synthesis: `Rser` adds a series resistor through an internal node; `Rpar` and `Cpar` add shunts across the resistor terminals. Core resistor model is unchanged. |
+| Capacitor instance parasitics `Rser`, `Lser`, `Rpar`, `Cpar` | Accepted in LTspice mode | Synthesizes helper R/L/C entities | OP/TRAN supported for R helpers and `Cpar`; `Lser` read fixture | Analytic/parser fixture | None expected for supported forms | Current parser/runtime | Parser-only topology synthesis: `Rser` and `Lser` add a series chain through internal nodes; `Rpar` and `Cpar` add shunts across the capacitor terminals. Core capacitor model is unchanged. |
+| Remaining inductor instance parasitics `Rser`, `Rpar`, `Cpar`, `Lser`, `RLshunt` | Accepted | Rejected in LTspice mode | Not runnable | None | Targeted LTspice instance-parameter error names parameter | Current parser/runtime | Topology-changing inductor parasitics are not synthesized yet; resistor/capacitor forms are tracked separately above. |
 | Capacitor `Q=<expr>` and inductor `Flux=<expr>` | Accepted | Core LTspice mode: targeted diagnostic. With `UseCustomComponents()`: produces `NonlinearCapacitor` / `NonlinearInductor`. | Custom components: TRAN and AC supported with operating-point incremental capacitance/inductance. | Focused parser/TRAN/AC fixtures plus optional LTspice-backed AC/TRAN golden comparisons | Core LTspice mode still emits targeted charge/flux diagnostic when custom mappings are not enabled | `SpiceSharpParser.CustomComponents` | `Q` uses `x` as terminal voltage and supports `IC`, `M`, and `N`; `Flux` uses `x` as branch current. Optional goldens compare AC small-signal voltage and transient waveform samples against LTspice when `LTSPICE_EXE` is configured. |
 | LTspice ideal diode parameters `Ron`, `Roff`, `Vfwd`, `Vrev`, `Rrev`, `Ilimit`, `RevIlimit`, `Epsilon`, `RevEpsilon` | Accepted | Core LTspice mode: targeted diagnostic. With `UseCustomComponents()`: produces `IdealDiodeModel` / `IdealDiode`. | Custom component: OP/DC/AC/TRAN supported as a memoryless nonlinear conductance. | Focused parser/integration/unit fixtures plus optional LTspice-backed DC sweep, AC, and rectifier-transient golden comparisons | Core LTspice mode still emits targeted ideal-diode diagnostics when custom mappings are not enabled | `SpiceSharpParser.CustomComponents` | These select LTspice's idealized diode behavior, not Berkeley diode parameters. The custom component supports model parameters, instance overrides, `M`/`N` scaling, `OFF`, and L/W model-bin selection; it does not model junction charge, capacitance, semiconductor noise, or temperature physics. |
 | Switch aliases `von`/`voff` and `ion`/`ioff` | Accepted | Lowered to `vt`/`vh` and `it`/`ih` | Existing switch model behavior | Read fixture | Missing pair or mixed native/alias forms are targeted errors | Current parser/runtime | Midpoint and half-span lowering only; no LTspice numeric parity claim. |

roadmap/ltspice-netlist-compatibility-plan.md

@@ -42,7 +42,7 @@ This roadmap is intentionally parser-first and evidence-first:
 - MOS model generation currently covers legacy levels 1, 2, and 3. LTspice `VDMOS` and advanced monolithic levels such as BSIM/EKV/HiSIM variants are runtime or intentional-unsupported candidates.
 - Distributed-line support currently starts from lossless `T`. LTspice lossy `O` / `LTRA` and uniform RC-line `URC` models need engine triage before runnable support is claimed.
 - P3 LTspice mode maps R/C model `tc=a[,b]`, switch `von`/`voff`, and current-switch `ion`/`ioff` aliases where they lower to existing parameters.
-- P3 LTspice mode warns on recognized metadata/rating parameters and emits targeted errors for topology-changing passive parasitics, ideal-diode parameters when custom mappings are not enabled, switch current-limiting/series options, `VDMOS`, high MOS levels, three-terminal power-MOS syntax, and `O` / `LTRA` / `U` / `URC` line families. The optional custom component package adds runnable `IdealDiode` support for LTspice-style diode parameters plus `NonlinearCapacitor` / `NonlinearInductor` support for LTspice-style capacitor `Q=` and inductor `Flux=` forms when `UseCustomComponents()` is enabled, with optional LTspice-backed DC/AC/transient golden comparisons when `LTSPICE_EXE` is configured.
+- P3 LTspice mode warns on recognized metadata/rating parameters, synthesizes resistor `Rser` / `Rpar` / `Cpar` and capacitor `Rser` / `Lser` / `Rpar` / `Cpar` helper topology, and emits targeted errors for remaining topology-changing passive parasitics, ideal-diode parameters when custom mappings are not enabled, switch current-limiting/series options, `VDMOS`, high MOS levels, three-terminal power-MOS syntax, and `O` / `LTRA` / `U` / `URC` line families. The optional custom component package adds runnable `IdealDiode` support for LTspice-style diode parameters plus `NonlinearCapacitor` / `NonlinearInductor` support for LTspice-style capacitor `Q=` and inductor `Flux=` forms when `UseCustomComponents()` is enabled, with optional LTspice-backed DC/AC/transient golden comparisons when `LTSPICE_EXE` is configured.
 
 ## Scope And Policy
 
@@ -239,12 +239,14 @@ Implemented P3 behavior:
 - Mapped R/C model `tc=a[,b]` aliases to `tc1` / `tc2`.
 - Mapped switch `von` / `voff` and current-switch `ion` / `ioff` aliases to midpoint/hysteresis parameters.
 - Warned on recognized LTspice metadata and rating parameters only in LTspice mode.
-- Added targeted diagnostics for topology-changing passive parasitics, LTspice ideal-diode parameters when custom mappings are not enabled, switch `Lser` / `Vser` / `Ilimit`, high MOS levels, `VDMOS`, three-terminal power-MOS syntax, and `O` / `LTRA` / `U` / `URC` line families. LTspice ideal-diode parameters, capacitor `Q=`, and inductor `Flux=` remain targeted diagnostics in core LTspice mode but are runnable through `SpiceSharpParser.CustomComponents` as `IdealDiode`, `NonlinearCapacitor`, and `NonlinearInductor`, with optional LTspice-backed DC/AC/transient golden evidence.
+- Added LTspice-mode parser synthesis for resistor instance parasitics: `Rser` adds a series resistor through an internal node, while `Rpar` and `Cpar` add shunts across the resistor terminals.
+- Added LTspice-mode parser synthesis for capacitor instance parasitics: `Rser` and `Lser` add a series helper chain through internal nodes, while `Rpar` and `Cpar` add shunts across the capacitor terminals.
+- Added targeted diagnostics for remaining topology-changing passive parasitics, LTspice ideal-diode parameters when custom mappings are not enabled, switch `Lser` / `Vser` / `Ilimit`, high MOS levels, `VDMOS`, three-terminal power-MOS syntax, and `O` / `LTRA` / `U` / `URC` line families. LTspice ideal-diode parameters, capacitor `Q=`, and inductor `Flux=` remain targeted diagnostics in core LTspice mode but are runnable through `SpiceSharpParser.CustomComponents` as `IdealDiode`, `NonlinearCapacitor`, and `NonlinearInductor`, with optional LTspice-backed DC/AC/transient golden evidence.
 
 Remaining follow-up:
 
 - Broaden model-family alias tables only when direct SpiceSharp equivalents are confirmed by fixtures.
-- Add engine work before claiming runnable support for `VDMOS`, advanced MOS families, lossy transmission lines, uniform RC lines, or synthesized passive parasitics.
+- Add engine or parser-synthesis work before claiming runnable support for `VDMOS`, advanced MOS families, lossy transmission lines, uniform RC lines, or remaining inductor passive parasitics.
 - Keep vendor-library import tests synthetic unless redistribution is clearly permitted.
 
 Initial model-family priorities: