Bits in the mip Register That Must Remain Zero Are Incorrectly Writable

[fly-1011]

Bug Description:

Because the NutShell processor does not implement the Hypervisor Extension, the mip register should follow the structure shown below:

Inconsistent information:

NutShell differs from Spike in bits 0, 2, 4, 6, 8, and 10. According to the RISCV specification, these bits should be 0.

Test program and log information: test_mip.zip

Environment:

NutShell: commit e315a27